ds2156gn Maxim Integrated Products, Inc., ds2156gn Datasheet - Page 212

• Manufacturer Part Number: ds2156gn
• Description: Ds2156, Ds2156l, Ds2156ln T1/e1/j1 Single-chip Transceiver Tdm/utopia Ii Interface
• Manufacturer: Maxim Integrated Products, Inc.

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 0 to 3/Error-Insertion Rate Select Bits (ER0 to ER3)
Bit 4/Constant Errors (CE). When this bit is set high (and the ER0 to ER3 bits are not set to 0000), the error-
insertion logic ignores the number-of-error registers (NOE1, NOE2) and generates errors constantly at the selected
insertion rate. When CE is set to 0, the NOEx registers determine how many errors are to be inserted.
Bits 5, 6/Unused, must be set to 0 for proper operation
Bit 7/Write NOE Registers (WNOE). If the host wishes to update to the NOEx registers, this bit must be toggled
from a 0 to a 1 after the host has already loaded the prescribed error count into the NOEx registers. The toggling of
this bit causes the error count loaded into the NOEx registers to be loaded into the error-insertion circuitry on the
next clock cycle. Subsequent updates require that the WNOE bit be set to 0 and then 1 once again.
ER3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
ER2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
WNOE
7
0
ER1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
ER0
—
ERC
Error-Rate Control Register
EBh
6
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
No errors inserted
1 in 16
1 in 32
1 in 64
1 in 128
1 in 256
1 in 512
1 in 1024
1 in 2048
1 in 4096
1 in 8192
1 in 16,384
1 in 32,768
1 in 65,536
1 in 131,072
1 in 262,144
—
Error Rate
5
0
CE
4
0
212 of 265
ER3
3
0
ER2
2
0
ER1
1
0
ER0
0
0