ds2156gn Maxim Integrated Products, Inc., ds2156gn Datasheet - Page 53

• Manufacturer Part Number: ds2156gn
• Description: Ds2156, Ds2156l, Ds2156ln T1/e1/j1 Single-chip Transceiver Tdm/utopia Ii Interface
• Manufacturer: Maxim Integrated Products, Inc.

8. T1 FRAMER/FORMATTER CONTROL AND STATUS REGISTERS
The T1 framer portion of the DS2156 is configured through a set of nine control registers. Typically, the
control registers are only accessed when the system is first powered up. Once the DS2156 has been
initialized, the control registers only need to be accessed when there is a change in the system
configuration. There are two receive control registers (T1RCR1 and T1RCR2), two transmit control
registers (T1TCR1 and T1TCR2), and a common control register (T1CCR1). Each of these registers is
described in this section.
8.1
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 0/Resynchronize (RESYNC). When toggled from low to high, a resynchronization of the receive-side framer
is initiated. Must be cleared and set again for a subsequent resync.
Bit 1/Sync Enable (SYNCE)
Bit 2/Sync Time (SYNCT)
Bit 3/Sync Criteria (SYNCC)
Bits 4, 5/Out-of-Frame Select Bits (OOF2, OOF1)
Bit 6/Auto Resync Criteria (ARC)
Bit 7/Unused, must be set to 0 for proper operation
OOF2
0
0
1
1
T1 Control Registers
0 = auto resync enabled
1 = auto resync disabled
0 = qualify 10 bits
1 = qualify 24 bits
In D4 Framing Mode:
0 = search for Ft pattern, then search for Fs pattern
1 = cross couple Ft and Fs pattern
In ESF Framing Mode:
0 = search for FPS pattern only
1 = search for FPS and verify with CRC6
0 = resync on OOF or RCL event
1 = resync on OOF only
—
OOF1
7
0
0
1
0
1
ARC
2/4 frame bits in error
2/5 frame bits in error
2/6 frame bits in error
2/6 frame bits in error
6
0
T1RCR1
T1 Receive Control Register 1
03h
Out-Of-Frame Criteria
OOF1
5
0
OOF2
4
0
53 of 265
SYNCC
3
0
SYNCT
2
0
SYNCE
1
0
RESYNC
0
0