ds2156gn Maxim Integrated Products, Inc., ds2156gn Datasheet - Page 67

• Manufacturer Part Number: ds2156gn
• Description: Ds2156, Ds2156l, Ds2156ln T1/e1/j1 Single-chip Transceiver Tdm/utopia Ii Interface
• Manufacturer: Maxim Integrated Products, Inc.

9.3
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 0/CAS Resync Criteria Met Event (CASRC). Set when two consecutive CAS MF alignment words are
received in error.
Bit 1/FAS Resync Criteria Met Event (FASRC). Set when three consecutive FAS words are received in error.
Bit 2/CRC Resync Criteria Met Event (CRCRC). Set when 915/1000 codewords are received in error.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 0/CRC4 MF Sync Active (CRC4SA). Set while the synchronizer is searching for the CRC4 MF alignment
word. This is a read-only, non-latched, real-time bit. It is not necessary to precede the read of this bit with a write.
Bit 1/CAS MF Sync Active (CASSA). Set while the synchronizer is searching for the CAS MF alignment word.
This is a read-only, non-latched, real-time bit. It is not necessary to precede the read of this bit with a write.
Bit 2/FAS Sync Active (FASSA). Set while the synchronizer is searching for alignment at the FAS level. This is a
read-only, non-latched, real-time bit. It is not necessary to precede the read of this bit with a write.
Bits 3 to 7/CRC4 Sync Counter Bits (CSC0, CSC2 to CSC4). The CRC4 sync counter increments each time the
8ms CRC4 multiframe search times out. The counter is cleared when the framer has successfully obtained
synchronization at the CRC4 level. The counter can also be cleared by disabling the CRC4 mode (E1RCR1.3 = 0).
This counter is useful for determining the amount of time the framer has been searching for synchronization at the
CRC4 level. ITU G.706 suggests that if synchronization at the CRC4 level cannot be obtained within 400ms, then
the search should be abandoned and proper action taken. The CRC4 sync counter rolls over. CSC0 is the LSB of
the 6-bit counter. (Note: The bit next to LSB is not accessible. CSC1 is omitted to allow resolution to >400ms
using 5 bits.) These are read-only, non-latched, real-time bits. It is not necessary to precede the read of these bits
with a write.
E1 Information Registers
CSC5
—
7
0
7
0
CSC4
6
0
—
INFO3
Information Register 3
12h
INFO7
Information Register 7 (Real-Time, Non-Latched Register)
30h
6
0
CSC3
5
0
—
5
0
CSC2
4
0
—
4
0
67 of 265
CSC0
3
0
—
3
0
FASSA
CRCRC
2
0
2
0
CASSA
FASRC
1
0
1
0
CRC4SA
CASRC
0
0
0
0