ds2156gn Maxim Integrated Products, Inc., ds2156gn Datasheet - Page 190

• Manufacturer Part Number: ds2156gn
• Description: Ds2156, Ds2156l, Ds2156ln T1/e1/j1 Single-chip Transceiver Tdm/utopia Ii Interface
• Manufacturer: Maxim Integrated Products, Inc.

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 0/Receive FIFO Overrun Interrupt Status (FOIS). Set if the receive FIFO overruns provided RxFIFO
overrun interrupt mask bit (U_RCR2.3) is set. This bit is reset when read.
Bit 1/LCD Change-of-State Interrupt Status (LCDCSIS). Set by hardware if LCD status changes, provided that
the LCD interrupt-mask bit (U_RCR2.4) is set. The LCDS bit indicates the current status of LCD. This bit is reset
when read.
Bit 2/LCD Status (LCDS)
Bit 3/Receiver Mode Status (RMS). This bit shows valid status only when HEC correction is enabled.
Bits 4, 5/Cell Delineation Status 0 to 1 (CDS0 to CDS1). Bit 5 indicates instantaneous OCD status.
Bits 6, 7/Unused
Once a read cycle to this register is detected, the interrupt status bits are cleared. If any of the lower two bits is set,
the external interrupt signal is asserted. If both the bits are 0 for all the ports, the external interrupt signal is de-
asserted.
CDS1
0
0
1
0 = in-cell delineation
1 = loss-of-cell delineation
0 = correction mode
1 = detection mode
CDS0
0
1
x
—
7
0
HUNT State
PRESYNC State
SYNC State
Cell Delineation Status
—
U_RSR
UTOPIA Receive Status Register
68h
6
0
CDS1
5
0
CDS0
4
0
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RMS
3
0
LCDS
2
1
LCDCSIS
1
0
FOIS
0
0