ds2156gn Maxim Integrated Products, Inc., ds2156gn Datasheet - Page 134

• Manufacturer Part Number: ds2156gn
• Description: Ds2156, Ds2156l, Ds2156ln T1/e1/j1 Single-chip Transceiver Tdm/utopia Ii Interface
• Manufacturer: Maxim Integrated Products, Inc.

Table 22-A. HDLC Controller Registers
H1TC, HDLC #1 Transmit Control Register
H2TC, HDLC #2 Transmit Control Register
H1RC, HDLC #1 Receive Control Register
H2RC, HDLC #2 Receive Control Register
H1FC, HDLC #1 FIFO Control Register
H2FC, HDLC #2 FIFO Control Register
SR6, HDLC #1 Status Register
SR7, HDLC #2 Status Register
IMR6, HDLC #1 Interrupt Mask Register
IMR7, HDLC #2 Interrupt Mask Register
INFO4, HDLC #1 and #2 Information Register
INFO5, HDLC #1 Information Register
INFO6, HDLC #2 Information Register
H1RPBA, HDLC #1 Receive Packet Bytes
Available Register
H2RPBA, HDLC #2 Receive Packet Bytes
Available Register
H1TFBA, HDLC #1 Transmit FIFO Buffer
Available Register
H2TFBA, HDLC #2 Transmit FIFO Buffer
Available Register
H1RCS1, H1RCS2, H1RCS3, H1RCS4, HDLC
#1 Receive Channel Select Registers
H2RCS1, H2RCS2, H2RCS3, H2RCS4, HDLC
#2 Receive Channel Select Registers
H1RTSBS, HDLC #1 Receive TS/Sa Bit Select
Register
H2RTSBS, HDLC #2 Receive TS/Sa Bit Select
Register
H1TCS1, H1TCS2, H1TCS3, H1TCS4, HDLC
#1 Transmit Channel Select Registers
H2TCS1, H2TCS2, H2TCS3, H2TCS4, HDLC
#2 Transmit Channel Select Registers
H1TTSBS, HDLC # 1 Transmit TS/Sa Bit Select
Register
H2TTSBS, HDLC # 2 Transmit TS/Sa Bit Select
Register
H1RF, HDLC #1 Receive FIFO Register
H2RF, HDLC #1 Receive FIFO Register
H1TF, HDLC #1 Transmit FIFO Register
H2TF, HDLC #2 Transmit FIFO Register
REGISTER
CONTROL AND CONFIGURATION
STATUS AND INFORMATION
MAPPING
FIFOs
134 of 265
General control over the transmit HDLC
controllers
General control over the receive HDLC
controllers
Sets high watermark for receiver and low
watermark for transmitter
Key status information for both transmit and
receive directions
Selects which bits in the status registers (SR7
and SR8) cause interrupts
Information about HDLC controller
Indicates the number of bytes that can be read
from the receive FIFO
Indicates the number of bytes that can be
written to the transmit FIFO
Selects which channels are mapped to the
receive HDLC controller
Selects which bits in a channel are used or
which Sa bits are used by the receive HDLC
controller
Selects which channels are mapped to the
transmit HDLC controller
Selects which bits in a channel are used or
which Sa bits are used by the transmit HDLC
controller
Access to 128-byte receive FIFO
Access to 128-byte transmit FIFO
FUNCTION
DS2156