ds2156gn Maxim Integrated Products, Inc., ds2156gn Datasheet - Page 183

• Manufacturer Part Number: ds2156gn
• Description: Ds2156, Ds2156l, Ds2156ln T1/e1/j1 Single-chip Transceiver Tdm/utopia Ii Interface
• Manufacturer: Maxim Integrated Products, Inc.

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 0 to 7/The host should always write 0x00 to this register when latching the PMON counter.
This register is provided for latching in the 16-bit transmit assigned cell-count value of a port into the common
transmit assigned cell-counter latch register. For reading the transmit assigned cell-count value, software writes
into this register and then reads from transmit-assigned cell-counter MSB and LSB registers. A write into this
register clears the transmit-assigned cell-count value.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 0 to 7/Transmit-Assigned Cell Count (TACC9 to TACC15)
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 0 to 7/Transmit-Assigned Cell Count (TACC0 to TACC7)
Transmit-assigned cell-count value reflects the number of ATM layer cells transmitted since last latching. For
reading the 16-bit transmit-assigned cell count for a port, software has to write into the transmit PMON-counter
latch-enable register for the port before reading these registers. Reading from these registers without writing into
the latch-enable register returns the old value that was latched and not the current MSB value.
TACC15
TACC7
—
7
7
0
0
7
0
TACC6
TACC14
—
U_TPCL
UTOPIA Transmit PMON Counter Latch Register
51h
U_TACC1
UTOPIA Transmit-Assigned Cell-Count Register 1
52h
U_TACC2
UTOPIA Transmit-Assigned Cell-Count Register 2
53h
6
0
6
0
6
0
TACC5
TACC13
—
5
0
5
0
5
0
TACC4
—
TACC12
4
0
4
0
4
0
183 of 265
TACC3
—
3
0
3
0
TACC11
3
0
TACC2
—
2
0
2
0
TACC10
2
0
TACC1
—
1
0
1
0
TACC9
1
0
TACC0
—
0
0
0
0
TACC8
0
0