ds2156gn Maxim Integrated Products, Inc., ds2156gn Datasheet - Page 213

• Manufacturer Part Number: ds2156gn
• Description: Ds2156, Ds2156l, Ds2156ln T1/e1/j1 Single-chip Transceiver Tdm/utopia Ii Interface
• Manufacturer: Maxim Integrated Products, Inc.

27.1 Number-of-Errors Registers
The number-of-error registers determine how many errors are generated. Up to 1023 errors can be
generated. The host loads the number of errors to be generated into the NOE1 and NOE2 registers. The
host can also update the number of errors to be created by first loading the prescribed value into the NOE
registers and then toggling the WNOE bit in the error-rate control registers.
Table 27-B. Error Insertion Examples
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 0 to 7/Number-of-Errors Counter Bits 0 to 7 (C0 to C7). Bit C0 is the LSB of the 10-bit counter.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 0, 1/Number-of-Errors Counter Bits 8 to 9 (C8 to C9). Bit C9 is the MSB of the 10-bit counter.
000h
001h
002h
3FFh
VALUE
Do not create any errors
Create a single error
Create two errors
Create 1023 errors
C7
—
7
7
0
0
WRITE
C6
—
NOE1
Number-of-Errors 1
ECh
NOE2
Number-of-Errors 2
EDh
6
0
6
0
C5
—
5
0
5
0
No errors left to be inserted
One error left to be inserted
Two errors left to be inserted
1023 errors left to be inserted
C4
—
4
0
4
0
213 of 265
READ
C3
—
3
0
3
0
C2
—
2
0
2
0
C1
C9
1
0
1
0
C0
C8
0
0
0
0