ds2156gn Maxim Integrated Products, Inc., ds2156gn Datasheet - Page 137

• Manufacturer Part Number: ds2156gn
• Description: Ds2156, Ds2156l, Ds2156ln T1/e1/j1 Single-chip Transceiver Tdm/utopia Ii Interface
• Manufacturer: Maxim Integrated Products, Inc.

22.2.1
The FIFO control register (HxFC) controls and sets the watermarks for the transmit and receive FIFOs.
Bits 3, 4, and 5 set the transmit low watermark and the lower 3 bits set the receive high watermark.
When the transmit FIFO empties below the low watermark, the TLWM bit in the appropriate HDLC
status register SR6 or SR7 is set. TLWM is a real-time bit and remains set as long as the transmit FIFO’s
read pointer is below the watermark. If enabled, this condition can also cause an interrupt through the INT
pin.
When the receive FIFO fills above the high watermark, the RHWM bit in the appropriate HDLC status
register is set. RHWM is a real-time bit and remains set as long as the receive FIFO’s write pointer is
above the watermark. If enabled, this condition can also cause an interrupt through the INT pin.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 0 to 2/Receive FIFO High-Watermark Select (RFHWM0 to RFHWM2)
Bits 3 to 5/Transmit FIFO Low-Watermark Select (TFLWM0 to TFLWM2)
Bits 6, 7/Unused, must be set to 0 for proper operation
RFHWM2
TFLWM2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
FIFO Control
—
7
0
RFHWM1
TFLWM1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
—
6
0
H1FC, H2FC
HDLC # 1 FIFO Control
HDLC # 2 FIFO Control
91h, A1h
RFHWM0
TFLWM0
TFLWM2
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
5
0
Transmit FIFO Watermark
Receive FIFO Watermark
TFLWM1
4
0
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(bytes)
(bytes)
112
112
16
32
48
64
80
96
16
32
48
64
80
96
4
4
TFLWM0
3
0
RFHWM2
2
0
RFHWM1
1
0
RFHWM0
0
0