MPC564MZP56 Freescale Semiconductor, MPC564MZP56 Datasheet - Page 1032

• Manufacturer Part Number: MPC564MZP56
• Description: IC MCU 512K FLASH 56MHZ 388-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Core: PowerPC
• Processor Series: MPC5xx
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 56 MHz
• Data Ram Size: 32 KB
• On-chip Adc: Yes
• Number Of Programmable I/os: 56
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 32
• Height: 1.95 mm
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Length: 27 mm
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 2.7 V, 5.25 V
• Supply Voltage (min): 2.5 V, 4.75 V
• Width: 27 mm
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

READI Module
24.10.3.2 Block Read Operation
For a block read access to memory-mapped locations and SPR registers, the following sequence of
operations need to be performed via the auxiliary port:
24.10.4 Read/Write Access to Internal READI Registers
24.10.4.1 Write Operation
For a write access to internal READI registers, the following sequence of operations need to be performed
via the auxiliary port:
24-64
4. Once the read access is completed, the upload/download information public message (TCODE =
5. The SC field in the RWA register is cleared.
1. The tool confirms that the device is ready before transmitting download request public message
2. The download request public message contains:
3. Data read from the specified address is stored in the UDI register.
4. After the completion of this read operation, the upload/download information public message
5. The specified address (in RWAD field) is incremented to the next word size and the number in the
6. The data read from the new address is stored in the UDI register.
7. Steps 4 through 7 are repeated until the count value in the CNT field of RWA register equals zero.
1. The tool confirms that the device is ready before transmitting download request public message
19) is transmitted to the tool along with the data read from the UDI register. This message also
indicates that the device is ready for next access.
(TCODE = 18).
a) TCODE(18)
b) Access opcode 0xF which signals that subsequent data needs to be stored in the RWA register.
c) Configure the RWA fields as follows:
(TCODE=19) is transmitted to the tool along with the data read from the UDI register. This
message also indicates that the device is ready to perform the next read operation.
CNT field is decremented. The SC field is not cleared.
The SC bit is cleared to indicate end of the block read access.
(TCODE = 18).
– Start/complete (1 to indicate start access) -> SC
– Read/write address (starting read address of block) -> RWAD
– Read/write (0 to indicate a read access) -> RW
– Word size (32 bits, 16 bits, 8 bits) -> SZ
– Write data (0xXXXXXXXX-> WD [don’t care])
– Privilege (user data/instruction, supervisor data/instruction) > PRV
– Map select (select memory map 0b0) -> MAP
– Access count (non-zero number to indicate block access) -> CNT
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor