MPC564MZP56 Freescale Semiconductor, MPC564MZP56 Datasheet - Page 709

IC MCU 512K FLASH 56MHZ 388-BGA

MPC564MZP56

Manufacturer Part Number
MPC564MZP56
Description
IC MCU 512K FLASH 56MHZ 388-BGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheets

Specifications of MPC564MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
56
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Core
PowerPC
Processor Series
MPC5xx
Data Bus Width
32 bit
Maximum Clock Frequency
56 MHz
Data Ram Size
32 KB
On-chip Adc
Yes
Number Of Programmable I/os
56
Number Of Timers
2
Operating Supply Voltage
0 V to 5 V
Mounting Style
SMD/SMT
A/d Bit Size
10 bit
A/d Channels Available
32
Height
1.95 mm
Interface Type
CAN, JTAG, QSPI, SCI, SPI, UART
Length
27 mm
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Supply Voltage (max)
2.7 V, 5.25 V
Supply Voltage (min)
2.5 V, 4.75 V
Width
27 mm
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No RoHS Version Available

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The user should prepare or change a message buffer for frame reception by executing the following steps.
Once these steps are performed, the message buffer functions as an active receive buffer and participates
in the internal matching process, which takes place every time the TouCAN receives an error-free frame.
In this process, all active receive buffers compare their ID value to the newly received one. If a match is
detected, the following actions occur:
The user should read a received frame from its message buffer in the following order:
If the free running timer is not read, that message buffer remains locked until the read process starts for
another message buffer. Only a single message buffer is locked at a time. When a received message is read,
the only mandatory read operation is that of the control/status word. This ensures data coherency.
If the BUSY bit is set in the message buffer code, the CPU should defer accessing that buffer until this bit
is negated. Refer to
Because the received identifier field is always stored in the matching receive message buffer, the contents
of the identifier field in a receive message buffer may change if one or more of the ID bits are masked.
Freescale Semiconductor
1. Write the control/status word to hold the receive buffer inactive (code = 0b0000)
2. Write the ID_HIGH and ID_LOW words
3. Write the control/status word to mark the receive message buffer as active and empty
1. The frame is transferred to the first (lowest entry) matching receive message buffer
2. The value of the free-running timer (captured at the beginning of the identifier field on the CAN
3. The ID field, data field, and Rx length field are stored
4. The code field is updated
5. The status flag is set in the IFLAG register
1. Control/status word (mandatory, as it activates the internal lock for this buffer)
2. ID (optional, since it is needed only if a mask was used)
3. Data field word(s)
4. Free-running timer (optional, as it releases the internal lock)
The user configures the message buffers for reception
The TouCAN transfers received messages from the serial message buffers to the receive message
buffers with matching IDs
The user retrieves these messages
bus) is written into the time stamp field in the message buffer
Steps 1 and 3 are mandatory for data coherency.
The user should check the status of a message buffer by reading the status
flag in the IFLAG register and not by reading the control/status word code
field for that message buffer. This prevents the buffer from being locked
inadvertently.
Table
16-2.
MPC561/MPC563 Reference Manual, Rev. 1.2
NOTE
NOTE
CAN 2.0B Controller Module
16-15

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