MPC564MZP56 Freescale Semiconductor, MPC564MZP56 Datasheet - Page 838

• Manufacturer Part Number: MPC564MZP56
• Description: IC MCU 512K FLASH 56MHZ 388-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Core: PowerPC
• Processor Series: MPC5xx
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 56 MHz
• Data Ram Size: 32 KB
• On-chip Adc: Yes
• Number Of Programmable I/os: 56
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 32
• Height: 1.95 mm
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Length: 27 mm
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 2.7 V, 5.25 V
• Supply Voltage (min): 2.5 V, 4.75 V
• Width: 27 mm
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

Time Processor Unit 3
Table 19-5
prescaler).
19.4
The TPU3 memory map contains three groups of registers:
All registers except the channel interrupt status register (CISR) must be read or written by means of
half-word (16-bit) or word (32-bit) accesses. The address space of the TPU3 memory map occupies 512
bytes. Unused registers within the 512-byte address space return zeros when read.
Table 19-6
19-8
•
•
•
System configuration registers
Channel control and status registers
Development support and test verification registers
TCR2 Value
TCR2PSCK2
CLOCK
DIV8
TCR2
Pin
Programming Model
is a summary of prescaler output (assuming a divide-by-one value for the pre-divider
shows the TPU3 address map.
0b00
0b01
0b10
0b11
0x30 4000(TPU_A)
0x30 4400(TPU_B)
0x30 4002(TPU_A)
0x30 4402(TPU_B)
0x30 4004(TPU_A)
0x30 4404(TPU_B)
0x30 4006(TPU_A)
0x30 4406(TPU_B)
Address
Control
TCR2PSCK2 = 0
Mux
Internal Clock Divide Ratio
16
32
64
8
MPC561/MPC563 Reference Manual, Rev. 1.2
Figure 19-4. TCR2 Prescaler Control
Table 19-5. TCR2 Prescaler Control
Clock
Source
Table 19-6. TPU3 Register Map
TPU3 Module Configuration Register (TPUMCR)
See
TPU3 Test Configuration Register (TCR)
Development Support Control Register (DSCR)
See
Development Support Status Register (DSSR)
See
Table 19-7
Table 19-8
Table 19-9
TCR2PSCK2 = 1
Pre-divider
Prescaler
120
24
56
8
for bit descriptions.
for bit descriptions.
for bit descriptions.
Register
TCR2PSCK2 = 0
Prescaler
TCR2
External Clock Divide Ratio
1
2
4
8
Freescale Semiconductor
TCR2PSCK2 = 1
TCR2
15
1
3
7