MPC564MZP56 Freescale Semiconductor, MPC564MZP56 Datasheet - Page 276

• Manufacturer Part Number: MPC564MZP56
• Description: IC MCU 512K FLASH 56MHZ 388-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Core: PowerPC
• Processor Series: MPC5xx
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 56 MHz
• Data Ram Size: 32 KB
• On-chip Adc: Yes
• Number Of Programmable I/os: 56
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 32
• Height: 1.95 mm
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Length: 27 mm
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 2.7 V, 5.25 V
• Supply Voltage (min): 2.5 V, 4.75 V
• Width: 27 mm
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

System Configuration and Protection
6-36
Reset
Reset
Field
Field
Addr
BASE
BASE + 4
BASE + 8
BASE + C
BASE +10
BASE + n
INTR:...
MSB
16
0
Save state
R3 ← @SIVEC
R4 ← Base of branch table
...
lbz RX, R3 (0)# load as byte
add RX, RX, R4
mtsprCTR, RX
bctr
Figure 6-23. Example of SIVEC Register Usage for Interrupt Table Handling
17
1
18
2
INTERRUPT CODE
b
b
b
b
Figure 6-22. SIU Interrupt Vector Register (SIVEC)
0011_1100
19
Routine1
Routine2
Routine3
Routine4
3
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MPC561/MPC563 Reference Manual, Rev. 1.2
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4
21
5
0000_0000_0000_0000
22
6
0x2F C01C
23
7
INTR:...
—
BASE
BASE + 400
BASE + 800
BASE + C00
BASE +1000
BASE + n
Save state
R3 ← @SIVEC
R4 ← Base of branch table
...
lhz RX, R3 (0)# load as half
add RX, RX, R4
mtspr CTR, RX
bctr
24
8
25
9
10
26
1st Instruction of Routine1
1st Instruction of Routine2
1st Instruction of Routine3
1st Instruction of Routine4
0000_0000
11
27
—
12
28
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Freescale Semiconductor
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29
14
30
LSB
15
31