MPC564MZP56 Freescale Semiconductor, MPC564MZP56 Datasheet - Page 187

• Manufacturer Part Number: MPC564MZP56
• Description: IC MCU 512K FLASH 56MHZ 388-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Core: PowerPC
• Processor Series: MPC5xx
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 56 MHz
• Data Ram Size: 32 KB
• On-chip Adc: Yes
• Number Of Programmable I/os: 56
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 32
• Height: 1.95 mm
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Length: 27 mm
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 2.7 V, 5.25 V
• Supply Voltage (min): 2.5 V, 4.75 V
• Width: 27 mm
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

When the operand falls in the range of double denormalized numbers it is considered a programming error.
The hardware will handle this case as if the operand was ZERO.
The following check is done on the stored operand in order to determine whether it is a denormalized
single-precision operand and invoke the floating-point assist interrupt handler:
Refer to the RCPU Reference Manual (Floating-Point Assist for Denormalized Operands) for complete
description of handling denormalized floating-point numbers.
3.13.10.8 Optional Instructions
No optional instructions are supported.
3.14
3.14.1
Both the lwarx and stwcx instructions are implemented according to the PowerPC ISA architecture
requirements. The MPC561/MPC563 does not provide support for snooping an external bus activity
outside the chip. The provision is made to cancel the reservation inside the MPC561/MPC563 by using the
CR and KR input signals. Internal buses are snooped for RCPU accesses, and the reservation mechanism
can be used for multitask single master applications.
3.14.2
The load/store unit hardware supports all of the PowerPC ISA load/store instructions. An optimal
performance is obtained for naturally aligned operands. These accesses result in optimal performance (one
bus cycle) for up to four bytes in size and good performance (two bus cycles) for double precision
floating-point operands. Unaligned operands are supported in hardware and are broken into a series of
aligned transfers. The effect of operand placement on performance is as stated in the VEA, except for the
case of 8-byte operands. In that case, since the RCPU uses a 32-bit wide data bus, the performance is good
rather than optimal.
3.14.3
The RCPU does not implement the following cache control instructions: icbi, dcbt, dcbi, dcbf, dcbz, dcbst,
and dcbtst .
3.14.4
The isync instruction causes a reflect which waits for all prior instructions to complete and then executes
the next sequential instruction. Any instruction after an isync will see all effects of prior instructions.
Freescale Semiconductor
Virtual Environment Architecture (VEA)
Atomic Update Primitives
Effect of Operand Placement on Performance
Storage Control Instructions
Instruction Synchronize (isync) Instruction
(frS[1:11]
MPC561/MPC563 Reference Manual, Rev. 1.2
≠
0) AND (frS[1:11]
≤
896)
Central Processing Unit
Eqn. 3-1
3-43