MPC564MZP56 Freescale Semiconductor, MPC564MZP56 Datasheet - Page 1266

• Manufacturer Part Number: MPC564MZP56
• Description: IC MCU 512K FLASH 56MHZ 388-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Core: PowerPC
• Processor Series: MPC5xx
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 56 MHz
• Data Ram Size: 32 KB
• On-chip Adc: Yes
• Number Of Programmable I/os: 56
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 32
• Height: 1.95 mm
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Length: 27 mm
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 2.7 V, 5.25 V
• Supply Voltage (min): 2.5 V, 4.75 V
• Width: 27 mm
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

Electrical Characteristics
F.13
Note: (T
F-50
56
57
58
59
60
61
62
63
66
67
68
69
70
A
= T
DSCK, DSDI
IEEE 1149.1 Electrical Characteristics
L
CLKOUT
SRESET
to T
H
)
TCK Falling Edge to Output Valid out of High Impedance
TCK Rising Edge to Boundary Scan Input Invalid
Boundary Scan Input Valid to TCK Rising Edge
TCK Falling Edge to Output High Impedance
Figure F-36. Reset Timing – Debug Port Configuration
TCK Clock Pulse Width Measured at V
TCK Low to TDO High Impedance
TCK Falling Edge to Output Valid
TCK Cycle Time
TCK Low to TDO Data Invalid
TCK Low to TDO Data Valid
MPC561/MPC563 Reference Manual, Rev. 1.2
TMS, TDI Data Setup Time
TMS, TDI Data Hold Time
TCK Rise and Fall Times
Characteristic
Table F-15. JTAG Timing
1
(JTAG clock)
53
44
54
DD
/2
55
Min
100
53
50
25
50
50
0
5
0
10 MHz
Freescale Semiconductor
Max
10
20
20
50
50
50
—
—
1
54
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns