MPC564MZP56 Freescale Semiconductor, MPC564MZP56 Datasheet - Page 514

• Manufacturer Part Number: MPC564MZP56
• Description: IC MCU 512K FLASH 56MHZ 388-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Core: PowerPC
• Processor Series: MPC5xx
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 56 MHz
• Data Ram Size: 32 KB
• On-chip Adc: Yes
• Number Of Programmable I/os: 56
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 32
• Height: 1.95 mm
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Length: 27 mm
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 2.7 V, 5.25 V
• Supply Voltage (min): 2.5 V, 4.75 V
• Width: 27 mm
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

QADC64E Legacy Mode Operation
The MCU IMB3 clock frequency is the basis of the QADC64E timing. The QADC64E requires that the
IMB3 clock frequency be at least twice the QCLK frequency. The QCLK frequency is established by the
combination of the PSH and PSL parameters in QACR0. The 5-bit PSH field selects the number of IMB3
clock cycles in the high phase of the QCLK wave. The 3-bit PSL field selects the number of IMB3 clock
cycles in the low phase of the QCLK wave.
Example 1 in
IMB3 clock and with PSL = 7 the QCLK remains low for 8 IMB3 clock cycles. Example 2 shows that
when PSH = 11, QCLK is high for 12 IMB3 clock cycles and with PSL = 7, QCLK is low for 8 IMB3
clock cycles. Finally, example 3 shows that with PSH = 7 and PSL = 7, QCLK alternates between high and
low every 8 IMB3 cycles.
13-50
QCLK EXAMPLES
Example
Number
IMB3 CLOCK
1
2
3
56 MHz EX1
40 MHz EX2
32 MHz EX3
Table 13-21
PSA is maintained for software compatibility but has no functional benefit
to this version of the module.
F
SYS
Frequency
56 MHz
40 MHz
32 MHz
Control Register 0 Information
Figure 13-25. QADC64E Clock Programmability Examples
shows that when the PSH = 19, the QCLK remains high for 20 cycles if the
Table 13-21. QADC64E Clock Programmability
MPC561/MPC563 Reference Manual, Rev. 1.2
PSH
19
11
7
PSA
NOTE
0
0
0
30 CYCLES
PSL
7
7
7
Input Sample Time (IST) =0b00
QCLK
(MHz)
2.0
2.0
2.0
QADC64E QCLK EX
Freescale Semiconductor
Conversion Time
(µs)
7.0
7.0
7.0