MPC564MZP56 Freescale Semiconductor, MPC564MZP56 Datasheet - Page 724
MPC564MZP56
Manufacturer Part Number
MPC564MZP56
Description
IC MCU 512K FLASH 56MHZ 388-BGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Specifications of MPC564MZP56
Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
56
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Core
PowerPC
Processor Series
MPC5xx
Data Bus Width
32 bit
Maximum Clock Frequency
56 MHz
Data Ram Size
32 KB
On-chip Adc
Yes
Number Of Programmable I/os
56
Number Of Timers
2
Operating Supply Voltage
0 V to 5 V
Mounting Style
SMD/SMT
A/d Bit Size
10 bit
A/d Channels Available
32
Height
1.95 mm
Interface Type
CAN, JTAG, QSPI, SCI, SPI, UART
Length
27 mm
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Supply Voltage (max)
2.7 V, 5.25 V
Supply Voltage (min)
2.5 V, 4.75 V
Width
27 mm
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No RoHS Version Available
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CAN 2.0B Controller Module
16.7.7
16-30
10:12
13:15
SRESET
Bits
8:15
Bits
0:7
0:7
8:9
Field
Addr
Control Register 2 (CANCTRL2)
CANCTRL2
PRESDIV
PRESDIV
MSB
PSEG1
PSEG2
Name
0
Name
RJW
1
0x30 7088 (CANCTRL2_A); 0x30 7488 (CANCTRL2_B); 0x30 7888 (CANCTRL2_C)
Prescaler divide factor. PRESDIV determines the ratio between the system clock frequency
and the serial clock (S-clock). The S-clock is determined by the following calculation:
The reset value of PRESDIV is 0x00, which forces the S-clock to default to the same
frequency as the system clock. The valid programmed values are 0 through 255.
See
See
Resynchronization jump width. The RJW field defines the maximum number of time quanta
a bit time may be changed during resynchronization. The valid programmed values are zero
through three.
The resynchronization jump width is calculated as follows:
PSEG1[2:0] — Phase buffer segment 1. The PSEG1 field defines the length of phase buffer
segment one in the bit time. The valid programmed values are zero through seven.
The length of phase buffer segment 1 is calculated as follows:
PSEG2 — Phase Buffer Segment 2. The PSEG2 field defines the length of phase buffer
segment two in the bit time. The valid programmed values are zero through seven.
The length of phase buffer segment two is calculated as follows:
2
Resynchronizaton Jump Width = (RJW + 1) Time Quanta
Phase Buffer Segment 1 = (PSEG1 + 1) Time Quanta
Phase Buffer Segment 2 = (PSEG2 + 1) Time Quanta
Table
Table
Figure 16-14. Control Register 2 (CANCTRL2)
PRESDIV
3
Table 16-18. CANCTRL2 Bit Descriptions
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 16-17. PRESDIV Bit Descriptions
16-18.
16-17.
4
5
0000_0000_0000_0000
6
S-clock
7
=
----------------------------------- -
PRESDIV
Description
Description
8
RJW
f SYS
9
+
1
10
PSEG1
11
12
Freescale Semiconductor
13
PSEG2
Eqn. 16-1
14
LSB
15
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