MPC564MZP56 Freescale Semiconductor, MPC564MZP56 Datasheet - Page 338

• Manufacturer Part Number: MPC564MZP56
• Description: IC MCU 512K FLASH 56MHZ 388-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Core: PowerPC
• Processor Series: MPC5xx
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 56 MHz
• Data Ram Size: 32 KB
• On-chip Adc: Yes
• Number Of Programmable I/os: 56
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 32
• Height: 1.95 mm
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Length: 27 mm
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 2.7 V, 5.25 V
• Supply Voltage (min): 2.5 V, 4.75 V
• Width: 27 mm
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

Clocks and Power Control
8.11.3
The COLIR is 16-bit read/write register. It controls the change of lock interrupt generation, and is used for
reporting a loss of lock interrupt source. It contains the interrupt request level and the interrupt status bit.
This register is readable and writable at any time. A status bit is cleared by writing a one (writing a zero
does not affect a status bit’s value). The COLIR is mapped into the MPC561/MPC563 USIU register map.
8-36
SRESET
27:31
11:15
Bits
Bits
Field
Addr
0:7
25
26
10
8
9
MSB
Change of Lock Interrupt Register (COLIR)
0
COLIRQ
LOLRE
COLIS
COLIE
Name
Name
DIVF
—
—
—
1
2
Loss of lock reset enable
0 Loss of lock does not cause HRESET assertion
1 Loss of lock causes HRESET assertion
Note: if limp mode is enabled, use the COLIR feature instead of setting the LOLRE bit. See
Section 8.11.3, “Change of Lock Interrupt Register
Reserved
The DIVF bits control the value of the pre-divider in the SPLL circuit. The DIVF bits can be
read and written at any time. However, the DIVF field can be write-protected by setting the
MF and pre-divider lock (MFPDL) bit in the SCCR. Changing the DIVF bits causes the SPLL
to lose lock.
Figure 8-18. Change of Lock Interrupt Register (COLIR)
Change of lock interrupt request level. These bits determine the interrupt priority level of the
change of lock. To specify a certain level, the appropriate one of these bits should be set.
If set (1), the bit indicates that a change in the PLL lock status was detected. The PLL was
locked and lost lock, or the PLL was unlocked and got locked. The bit should be cleared by
writing a one.
Reserved
Change of Lock Interrupt enable. If COLIE bit is asserted, an interrupt will be generated
when the COLIS bit is asserted.
0 Change of lock Interrupt disable
1 Change of lock Interrupt enable
Reserved
Table 8-11. PLPRCR Bit Descriptions (continued)
COLIRQ
3
MPC561/MPC563 Reference Manual, Rev. 1.2
0000_0000_00
Table 8-12. COLIR Bit Descriptions
4
5
6
0x2F C28C
7
COLIS
Description
Description
8
—
9
(COLIR).”
COLIE
10
11
Unaffected
12
Freescale Semiconductor
—
13
14
LSB
15