MPC564MZP56 Freescale Semiconductor, MPC564MZP56 Datasheet - Page 471

• Manufacturer Part Number: MPC564MZP56
• Description: IC MCU 512K FLASH 56MHZ 388-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Core: PowerPC
• Processor Series: MPC5xx
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 56 MHz
• Data Ram Size: 32 KB
• On-chip Adc: Yes
• Number Of Programmable I/os: 56
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 32
• Height: 1.95 mm
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Length: 27 mm
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 2.7 V, 5.25 V
• Supply Voltage (min): 2.5 V, 4.75 V
• Width: 27 mm
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

Table 13-4
multiplexer chips using one QADC module.
13.3
The QADC64E has three global registers for configuring module operation:
The global registers are always defined to be in supervisor-only data space. Refer to
QADC64E_A address map and
“Supervisor/Unrestricted Address
The remaining five registers in the control register block control the operation of the queuing mechanism,
and provide a means of monitoring the operation of the QADC64E.
Freescale Semiconductor
I
•
•
•
•
•
•
Module configuration register
(QADMCR)”)
Interrupt register
Test register (QADCTEST) for factory tests.
Control register 0 (QACR0) contains hardware configuration information
“Control Register 0
Control register 1 (QACR1) is associated with queue 1
(QACR1)”)
Control register 2 (QACR2) is associated with queue 2
(QACR2)”)
Programming the QADC64E Registers
shows the total number of analog input channels supported with zero to four external
No External
If either QADC64E_A or QADC64E_B is in external multiplexing
(EMUX) mode then the multiplexer address signal channels, AN[52:54]
should not be programmed into queues.
MUX Chips
16
Multiplexed Analog Input
(Section 13.3.2, “QADC64E Interrupt Register
Directly Connected + External Multiplexed = Total Channels
(QACR0)”)
NOTE: QADC64E External MUX Users
ANw (AN[0])
ANx (AN[1])
ANy (AN[2])
ANz (AN[3])
Table 13-3. Multiplexed Analog Input Channels
One External
MUX Chip
Table 13-2
MPC561/MPC563 Reference Manual, Rev. 1.2
Number of Analog Input Channels Available
Space” for access modes of these registers.
20
Table 13-4. Analog Input Channels
(Section 13.3.1, “QADC64E Module Configuration Register
for the QADC64E_B address map. See
Two External
MUX Chips
27
16, 18, 20, 22, 24, 26, 28, 30
17, 19, 21, 23, 25, 27, 29, 31
0, 2, 4, 6, 8, 10, 12, 14
1, 3, 5, 7, 9, 11, 13, 15
Channels
Three External
(Section 13.3.6, “Control Register 1
(Section 13.3.7, “Control Register 2
MUX Chips
34
(QADCINT)”
QADC64E Legacy Mode Operation
Four External
MUX Chips
(Section 13.3.5,
Section 13.3.1.4,
41
Table 13-1
for the
13-7