MPC564MZP56 Freescale Semiconductor, MPC564MZP56 Datasheet - Page 424

• Manufacturer Part Number: MPC564MZP56
• Description: IC MCU 512K FLASH 56MHZ 388-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Core: PowerPC
• Processor Series: MPC5xx
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 56 MHz
• Data Ram Size: 32 KB
• On-chip Adc: Yes
• Number Of Programmable I/os: 56
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 32
• Height: 1.95 mm
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Length: 27 mm
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 2.7 V, 5.25 V
• Supply Voltage (min): 2.5 V, 4.75 V
• Width: 27 mm
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

Memory Controller
10.6
The dual mapping feature also enables mapping of external memory to alternative memory regions
controlled by the memory controller. When dual mapping is enabled and an external address matches a
10-26
Dual Mapping of an External Flash Region
MPC5xx Memory Map
The default state is to allow dual-mapping data accesses only; this means
that dual mapping is possible only for data accesses on the internal bus.
Also, the default state takes the lower 2 Mbytes of the MPC563 internal
Flash memory. Hence, caution should be taken to change the dual-mapping
setup before the first data access. Dual mapping is not supported for an
external master when the memory controller serves the access; in such a
case, the MPC561/MPC563 terminates the cycle by asserting TEA.
Dual Mapping
External CSx
Flash
Figure 10-19. Aliasing Phenomenon Illustration
MPC561/MPC563 Reference Manual, Rev. 1.2
NOTE
CSx
Physical External Memory
Dual-Map region
Freescale Semiconductor