MPC564MZP56 Freescale Semiconductor, MPC564MZP56 Datasheet - Page 1051

IC MCU 512K FLASH 56MHZ 388-BGA

MPC564MZP56

Manufacturer Part Number
MPC564MZP56
Description
IC MCU 512K FLASH 56MHZ 388-BGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheets

Specifications of MPC564MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
56
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Core
PowerPC
Processor Series
MPC5xx
Data Bus Width
32 bit
Maximum Clock Frequency
56 MHz
Data Ram Size
32 KB
On-chip Adc
Yes
Number Of Programmable I/os
56
Number Of Timers
2
Operating Supply Voltage
0 V to 5 V
Mounting Style
SMD/SMT
A/d Bit Size
10 bit
A/d Channels Available
32
Height
1.95 mm
Interface Type
CAN, JTAG, QSPI, SCI, SPI, UART
Length
27 mm
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Supply Voltage (max)
2.7 V, 5.25 V
Supply Voltage (min)
2.5 V, 4.75 V
Width
27 mm
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No RoHS Version Available

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Figure 24-85
Freescale Semiconductor
Device sends
out Dev ID
msg after
negation of RSTI
MSEO
MDI
MSEI
HRESET
(Tool drives)
SRESET
(USIU drives)
RSTI
(Tool drives)
MDO
Figure 24-84. RCPU Development Access Timing Diagram — Debug Mode Entry Out-of-Reset
Tool negates
HRESET at least 16
system clocks after
receiving device
ready msg
1
Message
shows the transmission sequence of DSDI/DSDO data messages.
Dev ID
TC = 1
MSB
2
Config Msg
TCODE (6 bits)
TC = 18
DC reg. config
msg (BDM)
sent after DevID
msg received
by tool
(BDM)
DC reg
Figure 24-85. Transmission Sequence of DSDx Data Messages
1
3
Message
TC = 16
Device
Ready
LSB MSB
MPC561/MPC563 Reference Manual, Rev. 1.2
SRESET is negated by the MCU
HEADER (3 bits)
after some internal system clocks delay.
2
Message
TC = 58
BDM
ENTRY
4
BDM is set based on READI
module configuration
and BDM Entry msg is
sent out when VFLS[0:1]=11.
5
LSB MSB
DSDO msg
sent out
Message
TC = 56
DSDI msg
sent after.
BDM msg
DSDI
DATA (7 or 32 bits)
6
Message
TC = 57
DSDO
7
3
Message
TC = 56
DSDI
DSDI msg can be
sent to device after
TCODE and two
status bits in the
DSDO msg indicate
it is ready.
Message
TC = 57
DSDO
LSB
Message
TC = 58
BDM
EXIT
READI Module
24-83

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