MPC564MZP56 Freescale Semiconductor, MPC564MZP56 Datasheet - Page 674

• Manufacturer Part Number: MPC564MZP56
• Description: IC MCU 512K FLASH 56MHZ 388-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Core: PowerPC
• Processor Series: MPC5xx
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 56 MHz
• Data Ram Size: 32 KB
• On-chip Adc: Yes
• Number Of Programmable I/os: 56
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 32
• Height: 1.95 mm
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Length: 27 mm
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 2.7 V, 5.25 V
• Supply Voltage (min): 2.5 V, 4.75 V
• Width: 27 mm
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

Queued Serial Multi-Channel Module
looks for a possible start bit by watching for a high-to-low transition on the RXDx pin and by assigning
the RT time labels appropriately.
When the receiver is enabled by writing RE in SCCxR1 to one, the receiver bit pro-cessor logic begins an
asynchronous search for a start bit. The goal of this search is to gain synchronization with a frame. The
bit-time synchronization is done at the beginning of each frame so that small differences in the baud rate
of the receiver and transmitter are not cumulative. SCIx also synchronizes on all one-to-zero transitions in
the serial data stream, which makes SCIx tolerant to small frequency variations in the received data stream.
The sequence of events used by the receiver to find a start bit is listed below.
Upon detection of a valid start bit, synchronization is established and is maintained through the reception
of the last stop bit, after which the procedure starts all over again to search for a new valid start bit. During
a frame’s reception, SCIx resynchronizes the RT clock on any one-to-zero transitions.
Additional logic in the receiver bit processor determines the logic level of the received bit and implements
an advanced noise-detection function. During each bit-time of a frame (including the start and stop bits),
three logic-sense samples are taken at RT8, RT9, and RT10. The logic sense of the bit-time is decided by
a majority vote of these three samples. This logic level is shifted into register RDRx for every bit except
the start and stop bits.
If RT8, RT9, and RT10 do not all agree, an internal working noise flag is set. Additionally for the start bit,
if RT3, RT5, and RT7 do not all agree, the internal working noise flag is set. If this flag is set for any of
the bit-times in a frame, the NF flag in SCxSR is set concurrently with the RDRF flag in SCxSR when the
data is transferred to register RDRx. The user must determine if the data received with NF set is valid.
Noise on the RXDx pin does not necessarily corrupt all data.
15-56
1. Sample RXDx input during each RT period and maintain these samples in a serial pipeline that is
2. If RXDx is low during this RT period, go to step 1.
3. If RXDx is high during this RT period, store sample and proceed to step 4.
4. If RXDx is low during this RT period, but not high for the previous three RT periods (which is noise
5. If RXDx is low during this RT period and has been high for the previous three RT periods, call this
6. Skip RT2 but place RT3 in the pipeline and proceed to step 7.
7. Skip RT4 and sample RT5. If both RT3 and RT5 are high (RT1 was noise only), set an internal
8. Skip RT6 and sample RT7. If any two of RT3, RT5, or RT7 is high (RT1 was noise only), set an
9. A valid start bit is found and synchronization is achieved. From this point on until the end of the
three RT periods deep.
only), set an internal working noise flag and go to step 1, since this transition was not a valid start
bit transition.
period RT1, set RAF, and proceed to step 6.
working noise flag. Go to step 3 and clear RAF. Otherwise, place RT5 in the pipeline and proceed
to step 8.
internal working noise flag. Go to step 3 and clear RAF. Otherwise, place RT7 in the pipeline and
proceed to step 9.
frame, the RT clock will increment starting over again with RT1 on each one-to-zero transition or
each RT16. The beginning of a bit-time is thus defined as RT1 and the end of a bit-time as RT16.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor