MPC564MZP56 Freescale Semiconductor, MPC564MZP56 Datasheet - Page 723

• Manufacturer Part Number: MPC564MZP56
• Description: IC MCU 512K FLASH 56MHZ 388-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Core: PowerPC
• Processor Series: MPC5xx
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 56 MHz
• Data Ram Size: 32 KB
• On-chip Adc: Yes
• Number Of Programmable I/os: 56
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 32
• Height: 1.95 mm
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Length: 27 mm
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 2.7 V, 5.25 V
• Supply Voltage (min): 2.5 V, 4.75 V
• Width: 27 mm
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

16.7.6
Freescale Semiconductor
13:15
Bits
0:7
10
11
12
SRESET
8
9
Field
Addr
Prescaler Divide Register (PRESDIV)
CANCTRL0
PROPSEG
TSYNC
SAMP
Name
MSB
LBUF
0
—
—
1
0x30 7088 (PRESDIV_A); 0x30 7488 (PRESDIV_B); 0x30 7888 (PRESDIV_C)
See
Sampling mode. The SAMP bit determines whether the TouCAN module will sample each
received bit one time or three times to determine its value.
0 One sample, taken at the end of phase buffer segment one, is used to determine the value
1 Three samples are used to determine the value of the received bit. The samples are taken
Reserved
Timer synchronize mode. The TSYNC bit enables the mechanism that resets the
free-running timer each time a message is received in message buffer zero. This feature
provides the means to synchronize multiple TouCAN stations with a special “SYNC”
message (global network time).
0 Timer synchronization disabled.
1 Timer synchronization enabled.
Note: there can be a bit clock skew of four to five counts between different TouCAN modules
that are using this feature on the same network.
Lowest buffer transmitted first. The LBUF bit defines the transmit-first scheme.
0 Message buffer with lowest ID is transmitted first.
1 Lowest numbered buffer is transmitted first.
Reserved
Propagation segment time. PROPSEG defines the length of the propagation segment in the
bit time. The valid programmed values are zero to seven. The propagation segment time is
calculated as follows:
where
2
of the received bit.
at the normal sample point and at the two preceding periods of the S-clock.
Propagation Segment Time = (PROPSEG + 1) Time Quanta
1 Time Quantum = 1 Serial Clock (S-Clock) Period
Table 16-13
PRESDIV
Table 16-16. CANCTRL1 Bit Descriptions
MPC561/MPC563 Reference Manual, Rev. 1.2
3
Figure 16-13. Prescaler Divide Register
4
5
0000_0000_0000_0000
6
7
Description
8
9
10
CANCTRL2
11
12
CAN 2.0B Controller Module
13
14
LSB
15
16-29