MPC564MZP56 Freescale Semiconductor, MPC564MZP56 Datasheet - Page 499

IC MCU 512K FLASH 56MHZ 388-BGA

MPC564MZP56

Manufacturer Part Number
MPC564MZP56
Description
IC MCU 512K FLASH 56MHZ 388-BGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheets

Specifications of MPC564MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
56
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Core
PowerPC
Processor Series
MPC5xx
Data Bus Width
32 bit
Maximum Clock Frequency
56 MHz
Data Ram Size
32 KB
On-chip Adc
Yes
Number Of Programmable I/os
56
Number Of Timers
2
Operating Supply Voltage
0 V to 5 V
Mounting Style
SMD/SMT
A/d Bit Size
10 bit
A/d Channels Available
32
Height
1.95 mm
Interface Type
CAN, JTAG, QSPI, SCI, SPI, UART
Length
27 mm
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Supply Voltage (max)
2.7 V, 5.25 V
Supply Voltage (min)
2.5 V, 4.75 V
Width
27 mm
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No RoHS Version Available

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13.4.1.1
Total conversion time is made up of initial sample time, final sample time, and resolution time. Initial
sample time refers to the time during which the selected input channel is coupled through the buffer
amplifier to the sample capacitor. This buffer is used to quickly reproduce its input signal on the sample
capacitor and minimize charge sharing errors. During the final sampling period the amplifier is bypassed,
and the multiplexer input charges the sample capacitor array directly for improved accuracy. During the
resolution period, the voltage in the sample capacitor is converted to a digital value and stored in the SAR.
Initial sample time is fixed at two QCLK cycles. Final sample time can be 2, 4, 6, 8, or 16 QCLK cycles,
depending on the value of the IST field in the CCW. Resolution time is ten QCLK cycles.
Therefore, conversion time requires a minimum of 14 QCLK clocks (7 µs with a 2.0-MHz QCLK). If the
maximum final sample time period of 16 QCLKs is selected, the total conversion time is 28 QCLKs or 14
µs (with a 2.0-MHz QCLK)
Figure 13-21
13.4.1.2
If the amplifier bypass mode is enabled for a conversion by setting the amplifier bypass (BYP) bit in the
CCW, the timing changes to that shown in
the potential conversion time by two QCLKs. However, due to internal RC effects, a minimum final
sample time of four QCLKs must be allowed. This results in no savings of QCLKs. When using the bypass
mode, the external circuit should be of low source impedance, typically less than 10 kΩ. Also, the loading
effects of the external circuitry by the QADC64E need to be considered, since the benefits of the sample
amplifier are not present.
Freescale Semiconductor
QCLK
Conversion Cycle Times
Amplifier Bypass Mode Conversion Timing
illustrates the timing for conversions.
Because of internal RC time constants, a sample time of two QCLKs in
bypass mode for high frequency operation is not recommended.
2 cycles
Sample
BUFFER
Time
Sample TIME
Final Sample
(2, 4, 8, 16)
N cycles:
MPC561/MPC563 Reference Manual, Rev. 1.2
Time
Figure 13-21. Conversion Timing
Figure
Successive Approximation Resolution
13-22. The buffered sample time is eliminated, reducing
NOTE
Sequence
Resolution
10 cycles
Time
QADC64E Legacy Mode Operation
13-35

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