MPC564MZP56 Freescale Semiconductor, MPC564MZP56 Datasheet - Page 275

• Manufacturer Part Number: MPC564MZP56
• Description: IC MCU 512K FLASH 56MHZ 388-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Core: PowerPC
• Processor Series: MPC5xx
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 56 MHz
• Data Ram Size: 32 KB
• On-chip Adc: Yes
• Number Of Programmable I/os: 56
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 32
• Height: 1.95 mm
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Length: 27 mm
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 2.7 V, 5.25 V
• Supply Voltage (min): 2.5 V, 4.75 V
• Width: 27 mm
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

6.2.2.2.6
6.2.2.2.7
The SIEL is a 32-bit read/write register. Each pair of bits corresponds to an external interrupt request. The
EDx bit, if set, specifies that a falling edge in the corresponding IRQ line will be detected as an interrupt
request. When the EDx bit is 0, a low logical level in the IRQ line will be detected as an interrupt request.
The WMx (wake-up mask) bit, if set, indicates that an interrupt request detection in the corresponding line
causes the MPC561/MPC563 to exit low-power mode.
6.2.2.2.8
The SIVEC is a 32-bit read-only register that contains an 8-bit code representing the unmasked interrupt
source of the highest priority level. The SIVEC can be read as either a byte, half word, or word. When read
as a byte, a branch table can be used in which each entry contains one instruction (branch). When read as
a half-word, each entry can contain a full routine of up to 256 instructions. The interrupt code is defined
such that its two least significant bits are 0, thus allowing indexing into the table. The two possible ways
of the code usage are shown on
Freescale Semiconductor
SRESET
SRESET
HRESET
HRESET
Field
Field
Addr
Field ED0 WM0 ED1 WM1 ED2 WM2 ED3 WM3 ED4 WM4 ED5 WM5 ED6 WM6 ED7 WM7
Field
Addr
IRQ20
MSB
IMB
16
0
MSB
16
0
SIU Interrupt Mask Register 3 (SIMASK3)
SIU Interrupt Edge Level Register (SIEL)
SIU Interrupt Vector Register (SIVEC)
IRQ21
IMB
17
1
17
1
IRQ22
IMB
18
18
2
2
Figure 6-20. SIU Interrupt Mask Register 3 (SIMASK3)
Figure 6-21. SIU Interrupt Edge Level Register (SIEL)
IRQ23
19
IMB
3
19
3
Figure
MPC561/MPC563 Reference Manual, Rev. 1.2
IRQ
20
4
20
6
4
6-23.
LVL
21
5
6
21
5
IRQ24
IMB
22
6
0000_0000_0000_0000
0000_0000_0000_0000
0000_0000_0000_0000
0000_0000_0000_0000
22
6
IRQ25
IMB
0x2F C04C
0x2F C018
23
23
7
7
—
—
IRQ26
IMB
24
8
24
8
IRQ27
25
9
IMB
25
9
10
26
IRQ
10
26
7
LVL
System Configuration and Protection
11
27
11
27
7
IRQ28
IMB
12
28
12
28
IRQ29
IMB
13
29
13
29
IRQ30
IMB
14
30
14
30
IRQ31
LSB
15
31
IMB
LSB
15
31
6-35