MPC564MZP56 Freescale Semiconductor, MPC564MZP56 Datasheet - Page 633

• Manufacturer Part Number: MPC564MZP56
• Description: IC MCU 512K FLASH 56MHZ 388-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Core: PowerPC
• Processor Series: MPC5xx
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 56 MHz
• Data Ram Size: 32 KB
• On-chip Adc: Yes
• Number Of Programmable I/os: 56
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 32
• Height: 1.95 mm
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Length: 27 mm
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 2.7 V, 5.25 V
• Supply Voltage (min): 2.5 V, 4.75 V
• Width: 27 mm
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

Serial transfers of eight to 16 bits can be specified. Programmable transfer length simplifies interfacing to
devices that require different data lengths.
An inter-transfer delay of approximately 0.8 to 204 µs (using a 40-MHz IMB3 clock) can be programmed.
The default delay is 17 clocks (0.425 µs at 40 MHz). Programmable delay simplifies the interface to
devices that require different delays between transfers.
Freescale Semiconductor
Queue Control
Programmable
Comparator
Logic Array
End Queue
Register
Registers
Counter
Control
Pointer
Control
Delay
Pointer
Status
Block
Queue
Logic
4
Done
MPC561/MPC563 Reference Manual, Rev. 1.2
Figure 15-10. QSPI Block Diagram
4
4
4
Chip Select
G
A
D
D
R
E
S
S
R
E
S
T
E
R
I
Command
MSB
8/16-bit Shift Register
Rx / Tx Data Register
Rx Data
QSPI RAM
160-Byte
2
Tx Data
LSB
Baud Rate
Generator
Queued Serial Multi-Channel Module
M
M
S
S
QSPI Block
MOSI
MISO
PCS0/SS
PCS[2:1]
SCK
15-15