MPC564MZP56 Freescale Semiconductor, MPC564MZP56 Datasheet - Page 166

• Manufacturer Part Number: MPC564MZP56
• Description: IC MCU 512K FLASH 56MHZ 388-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Core: PowerPC
• Processor Series: MPC5xx
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 56 MHz
• Data Ram Size: 32 KB
• On-chip Adc: Yes
• Number Of Programmable I/os: 56
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 32
• Height: 1.95 mm
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Length: 27 mm
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 2.7 V, 5.25 V
• Supply Voltage (min): 2.5 V, 4.75 V
• Width: 27 mm
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

Central Processing Unit
The floating-point exception mode bits are interpreted as shown in
3.9.2
The DSISR, SPR 18, identifies the cause of data access and alignment exceptions.
For more information about bit settings, see
Section 3.15.4.6, “Alignment Exception
Data Protection Error Exception
3-22
Reset
Bits
Field
Addr
27
28
29
30
31
MSB
DAE/Source Instruction Service Register (DSISR)
0
DCMPEN Decompression On/Off. The reset value of this bit is (BBCMCR[EN_COMP] AND
Name
DR
LE
—
RI
1
01, 10, 11
2
FE[0:1]
Table 3-11. Machine State Register Bit Descriptions (continued)
00
3
Figure 3-12. DAE/Source Instruction Service Register (DSISR)
Data relocation.
0 Data address translation is off; the L2U DMPU does not check for address permission
1 Data address translation is on; the L2U DMPU checks for addressn permission attributes.
Reserved
BBCMCR[EXC_COMP]).
Note: This bit should not be set for the MPC561/MPC563.
0 The RCPU runs in normal operation mode.
1 The RCPU runs in compressed mode.
Note: MSR[DCMPEN] should not be changed by software by a direct MSR register write
Recoverable exception (for machine check and non-maskable breakpoint exceptions).
0 Machine state is not recoverable.
1 Machine state is recoverable.
Little-endian mode. This mode is not supported on MPC561/MPC563. This bit should be
cleared to 0 at all times.
0 The processor operates in big-endian mode during normal processing.
1 The processor operates in little-endian mode during normal processing.
4
attributes.
5
(MTMSR instruction). It can be changed only by the RFI instruction or by an exception.
6
floating-point assist error handler to be invoked.
handler is invoked precisely at the instruction that caused the enabled
exception.
Ignore exceptions mode. Floating-point exceptions do not cause the
Floating-point precise mode. The system floating-point assist error
Table 3-12. Floating-Point Exception Mode Bits
7
MPC561/MPC563 Reference Manual, Rev. 1.2
(0x1400).”
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
(0x00600),” and
Section 3.15.4.2, “Machine Check Exception
Unchanged
SPR 18
DSISR
Mode
Description
Section 3.15.4.15, “Implementation-Specific
Table
3-12.
Freescale Semiconductor
(0x0200),”
LSB
31