MPC564MZP56 Freescale Semiconductor, MPC564MZP56 Datasheet - Page 677

IC MCU 512K FLASH 56MHZ 388-BGA

MPC564MZP56

Manufacturer Part Number
MPC564MZP56
Description
IC MCU 512K FLASH 56MHZ 388-BGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheets

Specifications of MPC564MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
56
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Core
PowerPC
Processor Series
MPC5xx
Data Bus Width
32 bit
Maximum Clock Frequency
56 MHz
Data Ram Size
32 KB
On-chip Adc
Yes
Number Of Programmable I/os
56
Number Of Timers
2
Operating Supply Voltage
0 V to 5 V
Mounting Style
SMD/SMT
A/d Bit Size
10 bit
A/d Channels Available
32
Height
1.95 mm
Interface Type
CAN, JTAG, QSPI, SCI, SPI, UART
Length
27 mm
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Supply Voltage (max)
2.7 V, 5.25 V
Supply Voltage (min)
2.5 V, 4.75 V
Width
27 mm
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No RoHS Version Available

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A receiver is placed in wake-up mode by setting the RWU bit in SCCxR1. While RWU is set, receiver
status flags and interrupts are disabled. Although the software can clear RWU, it is normally cleared by
hardware during wake-up.
The WAKE bit in SCCxR1 determines which type of wake-up is used. When WAKE = 0, idle-line wake-up
is selected. When WAKE = 1, address-mark wake-up is selected. Both types require a software-based
device addressing and recognition scheme.
Idle-line wake-up allows a receiver to sleep until an idle line is detected. When an idle line is detected, the
receiver clears RWU and wakes up. The receiver waits for the first frame of the next transmission. The
data frame is received normally, transferred to the RDRx, and the RDRF flag is set. If software does not
recognize the address, it can set RWU and put the receiver back to sleep. For idle-line wake-up to work,
there must be a minimum of one frame of idle line between transmissions. There must be no idle time
between frames within a transmission.
Address mark wake-up uses a special frame format to wake up the receiver. When the MSB of an
address-mark frame is set, that frame contains address information. The first frame of each transmission
must be an address frame. When the MSB of a frame is set, the receiver clears RWU and wakes up. The
data frame is received normally, transferred to the RDRx, and the RDRF flag is set. If software does not
recognize the address, it can set RWU and put the receiver back to sleep. Address mark wake-up allows
idle time between frames and eliminates idle time between transmissions. However, there is a loss of
efficiency because of an additional bit-time per frame.
15.7.7.11 Internal Loop Mode
The LOOPS bit in SCCxR1 controls a feedback path in the data serial shifter. When LOOPS is set, the SCI
transmitter output is fed back into the receive serial shifter. TXD is asserted (idle line). Both transmitter
and receiver must be enabled before entering loop mode.
15.8
15.8.1
The SCI1 serial module allows for queueing on transmit and receive data frames. In the standard mode, in
which the queue is disabled, the SCI1 operates as previously defined (i.e., transmit and receive operations
done via SC1DR). However, if the SCI1 queue feature is enabled (by setting the QTE and/or QRE bits
within QSCI1CR) a set of 16 entry queues is allocated for the receive and/or transmit operation. Through
software control the queue is capable of continuous receive and transfer operations within the SCI1 serial
unit.
15.8.2
The SCI1 queue uses the following registers:
Freescale Semiconductor
QSCI1 control register (QSCI1CR, address offset 0x28)
QSCI1 status register (QSCI1SR, address offset 0x2A)
SCI Queue Operation
Queue Operation of SCI1 for Transmit and Receive
Queued SCI1 Status and Control Registers
MPC561/MPC563 Reference Manual, Rev. 1.2
Queued Serial Multi-Channel Module
15-59

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