MPC564MZP56 Freescale Semiconductor, MPC564MZP56 Datasheet - Page 58

• Manufacturer Part Number: MPC564MZP56
• Description: IC MCU 512K FLASH 56MHZ 388-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Core: PowerPC
• Processor Series: MPC5xx
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 56 MHz
• Data Ram Size: 32 KB
• On-chip Adc: Yes
• Number Of Programmable I/os: 56
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 32
• Height: 1.95 mm
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Length: 27 mm
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 2.7 V, 5.25 V
• Supply Voltage (min): 2.5 V, 4.75 V
• Width: 27 mm
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

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Figure
Number
Option A Power-Up Sequence With Keep-Alive Supply....................................................... F-14
Option A Power-Down Sequence Without Keep-Alive Supply............................................. F-15
Option A Power-Down Sequence With Keep-Alive Supply.................................................. F-15
Option B Power-Up Sequence Without Keep-Alive Supply.................................................. F-16
Option B Power-Up Sequence With Keep-Alive Supply ....................................................... F-16
Option B Power-Down Sequence Without Keep-Alive Supply ............................................. F-17
Option B Power-Down Sequence with Keep-Alive Supply ................................................... F-17
Generic Timing Examples ...................................................................................................... F-19
CLKOUT Pin Timing ............................................................................................................. F-27
Synchronous Output Signals Timing ...................................................................................... F-28
Predischarge Timing ............................................................................................................... F-29
Synchronous Active Pull-Up And Open Drain
Outputs Signals Timing .......................................................................................................... F-30
Synchronous Input Signals Timing......................................................................................... F-31
Input Data Timing In Normal Case ........................................................................................ F-32
External Bus Read Timing (GPCM Controlled – ACS = ‘00’).............................................. F-33
External Bus Read Timing (GPCM Controlled – TRLX = ‘0’ ACS = ‘10’).......................... F-34
External Bus Read Timing (GPCM Controlled – TRLX = ‘0’ ACS = ‘11’).......................... F-35
External Bus Read Timing (GPCM Controlled – TRLX = ‘1’, ACS = ‘10’, ACS = ‘11’).... F-36
Address Show Cycle Bus Timing ........................................................................................... F-36
Address and Data Show Cycle Bus Timing............................................................................ F-37
External Bus Write Timing (GPCM Controlled – TRLX = ‘0’, CSNT = ‘0’) ....................... F-38
External Bus Write Timing (GPCM Controlled – TRLX = ‘0’, CSNT = ‘1’) ....................... F-39
External Bus Write Timing (GPCM Controlled – TRLX = ‘1’, CSNT = ‘1’) ....................... F-40
External Master Read From Internal Registers Timing.......................................................... F-41
External Master Write To Internal Registers Timing ............................................................. F-42
Interrupt Detection Timing for External Edge Sensitive Lines .............................................. F-43
Debug Port Clock Input Timing ............................................................................................. F-44
Debug Port Timings................................................................................................................ F-44
Auxiliary Port Data Input Timing Diagram............................................................................ F-45
Auxiliary Port Data Output Timing Diagram ......................................................................... F-46
Enable Auxiliary From RSTI.................................................................................................. F-46
Disable Auxiliary From RSTI................................................................................................. F-46
Reset Timing – Configuration from Data Bus........................................................................ F-48
Reset Timing – Data Bus Weak Drive During Configuration................................................ F-49
Reset Timing – Debug Port Configuration ............................................................................. F-50
JTAG Test Clock Input Timing .............................................................................................. F-51
JTAG Test Access Port Timing Diagram ............................................................................... F-52
Boundary Scan (JTAG) Timing Diagram............................................................................... F-53
QSPI Timing – Master, CPHA = 0 ......................................................................................... F-58
MPC561/MPC563 Reference Manual, Rev. 1.2
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