MPC564MZP56 Freescale Semiconductor, MPC564MZP56 Datasheet - Page 859

IC MCU 512K FLASH 56MHZ 388-BGA

MPC564MZP56

Manufacturer Part Number
MPC564MZP56
Description
IC MCU 512K FLASH 56MHZ 388-BGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheets

Specifications of MPC564MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
56
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Core
PowerPC
Processor Series
MPC5xx
Data Bus Width
32 bit
Maximum Clock Frequency
56 MHz
Data Ram Size
32 KB
On-chip Adc
Yes
Number Of Programmable I/os
56
Number Of Timers
2
Operating Supply Voltage
0 V to 5 V
Mounting Style
SMD/SMT
A/d Bit Size
10 bit
A/d Channels Available
32
Height
1.95 mm
Interface Type
CAN, JTAG, QSPI, SCI, SPI, UART
Length
27 mm
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Supply Voltage (max)
2.7 V, 5.25 V
Supply Voltage (min)
2.5 V, 4.75 V
Width
27 mm
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No RoHS Version Available

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address of the array should be written in a single operation. Writing only one half of the register will
prevent the other half from being written.
20.3.4
The MISRH and MISRL together contain the 32-bit RAM signature calculated by the MISC. These
registers are read-only and should be read by the host when the MISF bit in the MCR is set.
Exiting TPU3 emulation mode results in the reset of both MISRH and MISRL.
Freescale Semiconductor
SRESET
SRESET
12:14
Bits
0:11
15
Field
Addr
Field
Addr
MISR High (MISRH) and MISR Low Registers (MISRL)
RAMDS
D31
A[8:19]
MSB
Name
MSB
0
A8
0
D30 D29
1
A9
1
DPTRAM array base address. These bits specify the 11 high-order bits of the 24-bit base
address of the DPTRAM array. This allows the array to be placed on a 8-Kbyte boundary
anywhere in the memory map. Do not overlap the DPTRAM array memory map with other
modules on the chip.
On the MPC561/MPC563 the value 0xFFA0 must be used for DPTRAM 6 Kbyte.
Reserved. (Bit 12 represents A[20] in DPTRAM implementations that require it.)
RAM disabled. RAMDS is a read-only status bit. The DPTRAM array is disabled after a master
reset because the RAMBAR register may be incorrect. When the array is disabled, it will not
respond to any addresses on the IMB3. Access to the DPTRAM control register block is not
affected when the array is disabled.
RAMDS is cleared by the DPTRAM module when a base address is written to the array address
field of RAMBAR.
RAMDS = 0: DPTRAM enabled
RAMDS = 1: DPTRAM disabled
Figure 20-5. Multiple Input Signature Register High (MISRH)
Figure 20-4. RAM Array Base Address Register (RAMBAR)
2
A10
2
D28
3
A11
MPC561/MPC563 Reference Manual, Rev. 1.2
3
Table 20-3. RAMBAR Bit Settings
D27
4
A12
4
D26
5
0000_0000_0000_000
A13
5
D25
0000_0000_0000_0000
6
A14
6
D24
0x30 0006
0x30 0004
7
A15
7
Description
D23 D22 D21 D20
8
A16
8
9
A17
9
10
A18
10
11
A19
11
D19
Dual-Port TPU3 RAM (DPTRAM)
12
12
D18
13
13
D17
14
14
RAMDS
LSB
D16
15
LSB
1
15
20-5

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