MPC564MZP56 Freescale Semiconductor, MPC564MZP56 Datasheet - Page 399
MPC564MZP56
Manufacturer Part Number
MPC564MZP56
Description
IC MCU 512K FLASH 56MHZ 388-BGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Specifications of MPC564MZP56
Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
56
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Core
PowerPC
Processor Series
MPC5xx
Data Bus Width
32 bit
Maximum Clock Frequency
56 MHz
Data Ram Size
32 KB
On-chip Adc
Yes
Number Of Programmable I/os
56
Number Of Timers
2
Operating Supply Voltage
0 V to 5 V
Mounting Style
SMD/SMT
A/d Bit Size
10 bit
A/d Channels Available
32
Height
1.95 mm
Interface Type
CAN, JTAG, QSPI, SCI, SPI, UART
Length
27 mm
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Supply Voltage (max)
2.7 V, 5.25 V
Supply Voltage (min)
2.5 V, 4.75 V
Width
27 mm
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No RoHS Version Available
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Chapter 10
Memory Controller
The memory controller generates interface signals to support a glueless interface to external memory and
peripheral devices. It supports four regions, each with its own programmed attributes. The four regions are
controlled by four chip-select signals. Read and write strobes are also provided.
The memory controller operates in parallel with the external bus interface to support external cycles. When
an access to one of the memory regions is initiated, the memory controller takes ownership of the external
signals and controls the access until its termination. Refer to
10.1
The memory controller provides a glueless interface to external EPROM, static RAM (SRAM), Flash
(EEPROM), and other peripherals. The general-purpose chip-selects are available on lines CS0 through
CS3. CS0 also functions as the global (boot) chip-select for accessing the boot Flash EEPROM. The chip
select allows zero to 30 wait states.
Figure 10-2
Freescale Semiconductor
Internal Bus
Overview
is a block diagram of the MPC561/MPC563 memory controller.
Interface
U-bus
Figure 10-1. Memory Controller Function within the USIU
MPC561/MPC563 Reference Manual, Rev. 1.2
Memory Controller
EBI Bus
Bus
External Bus
Controller
Figure
Memory
Interface
10-1.
ADDR[0:31]
DATA[0:31]
Control Bus
WE[0:3]/BE[0:3]
OE
CS[0:3]
10-1
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