MPC564MZP56 Freescale Semiconductor, MPC564MZP56 Datasheet - Page 382
MPC564MZP56
Manufacturer Part Number
MPC564MZP56
Description
IC MCU 512K FLASH 56MHZ 388-BGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Specifications of MPC564MZP56
Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
56
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Core
PowerPC
Processor Series
MPC5xx
Data Bus Width
32 bit
Maximum Clock Frequency
56 MHz
Data Ram Size
32 KB
On-chip Adc
Yes
Number Of Programmable I/os
56
Number Of Timers
2
Operating Supply Voltage
0 V to 5 V
Mounting Style
SMD/SMT
A/d Bit Size
10 bit
A/d Channels Available
32
Height
1.95 mm
Interface Type
CAN, JTAG, QSPI, SCI, SPI, UART
Length
27 mm
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Supply Voltage (max)
2.7 V, 5.25 V
Supply Voltage (min)
2.5 V, 4.75 V
Width
27 mm
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No RoHS Version Available
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External Bus Interface
9.5.10
Reservation occurs when a master loads data from memory. The memory location must not be overwritten
until the master finishes processing the data and writing the results back to the reserved location. The
MPC561/MPC563 storage reservation protocol supports a multi-level bus structure. For each local bus,
storage reservation is handled by the local reservation logic.
The protocol tries to optimize reservation cancellation such that an MPC500 processor is notified of
storage reservation loss on a remote bus only when it has issued a conditional storeword (stwcx) cycle to
that address. That is, the reservation loss indication comes as part of the stwcx cycle. This method avoids
the need to have very fast storage reservation loss indication signals routed from every remote bus to every
MPC500 master.
The storage reservation protocol makes the following assumptions:
The reservation protocol for a single-level (local) bus is illustrated in
that an external logic on the bus carries out the following functions:
9-42
•
•
•
•
•
•
•
•
•
•
•
Each processor has, at most, one reservation flag
lwarx sets the reservation flag
lwarx by the same processor clears the reservation flag related to a previous lwarx instruction and
again sets the reservation flag
stwcx by the same processor clears the reservation flag
Store by the same processor does not clear the reservation flag
Some other processor (or other mechanism) store to the same address as an existing reservation
clears the reservation flag
In case the storage reservation is lost, it is guaranteed that stwcx will not modify the storage
Snoops accesses to all local bus slaves
Holds one reservation for each local master capable of storage reservations
Sets the reservation when that master issues a load and reserve request
Clears the reservation when some other master issues a store to the reservation address
Storage Reservation
MPC561/MPC563 Reference Manual, Rev. 1.2
Figure
9-30. The protocol assumes
Freescale Semiconductor
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