MPC564MZP56 Freescale Semiconductor, MPC564MZP56 Datasheet - Page 355

• Manufacturer Part Number: MPC564MZP56
• Description: IC MCU 512K FLASH 56MHZ 388-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Core: PowerPC
• Processor Series: MPC5xx
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 56 MHz
• Data Ram Size: 32 KB
• On-chip Adc: Yes
• Number Of Programmable I/os: 56
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 32
• Height: 1.95 mm
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Length: 27 mm
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 2.7 V, 5.25 V
• Supply Voltage (min): 2.5 V, 4.75 V
• Width: 27 mm
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

1. For an illustration of device connections on the data bus, see
9.5.3
Pre-discharge mode is provided for applications that use 3.3-V/5-V external memories while the
MPC561/MPC563 data bus pads are optimized to 2.6-V memories, and cannot tolerate more than 3.1 V.
When connecting 3.3-V devices to the E-bus, and performing read and write operations, this mode should
be invoked in order to avoid long term reliability issues of the data pads.
When the PDMCR2[PREDIS_EN] bit is set, the MPC561/MPC563 will discharge the bus during the
address phase of any write cycle prior to the data phase. The data bus will be discharged from up to 5 V to
a level which is suitable to the low voltage drivers. In most cases, the ORx[EHTR] bit of the relevant
memory bank, should be set along with the PREDIS_EN bit in order to reserve sufficient time for the
Freescale Semiconductor
CLKOUT
BR
BG
BB
ADDR[0:1]
RD/WR
TSIZ[0:1]
BURST, BDIP
TS
STS
Data
TA
1
Data Bus Pre-Discharge Mode
Figure 9-10. Single Beat 32-Bit Data Write Cycle Timing — 16-Bit Port Size
MPC561/MPC563 Reference Manual, Rev. 1.2
ADDR
00
ABCDEFGH
Figure
9-23.
10
ADDR + 2
EFGHEFGH
External Bus Interface
9-15