MPC564MZP56 Freescale Semiconductor, MPC564MZP56 Datasheet - Page 750
MPC564MZP56
Manufacturer Part Number
MPC564MZP56
Description
IC MCU 512K FLASH 56MHZ 388-BGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Specifications of MPC564MZP56
Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
56
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Core
PowerPC
Processor Series
MPC5xx
Data Bus Width
32 bit
Maximum Clock Frequency
56 MHz
Data Ram Size
32 KB
On-chip Adc
Yes
Number Of Programmable I/os
56
Number Of Timers
2
Operating Supply Voltage
0 V to 5 V
Mounting Style
SMD/SMT
A/d Bit Size
10 bit
A/d Channels Available
32
Height
1.95 mm
Interface Type
CAN, JTAG, QSPI, SCI, SPI, UART
Length
27 mm
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Supply Voltage (max)
2.7 V, 5.25 V
Supply Voltage (min)
2.5 V, 4.75 V
Width
27 mm
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No RoHS Version Available
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Modular Input/Output Subsystem (MIOS14)
17.7.3.2
17-18
SRESET
12:15
Bits
2:11
0
1
Field PREN FREN
Addr
MSB
PSL[3:0]
MCPSM Status/Control Register (MCPSMSCR)
0
Name
PREN
FREN
If the binary value 0b0001 is entered in PSL[3:0], the output signal is stuck
at zero, no clock is output.
—
1
Prescaler enable bit — This active high read/write control bit enables the MCPSM counter. The
PREN bit is cleared by reset.
0 MCPSM counter disabled.
1 MCPSM counter enabled.
Freeze bit — This active high read/write control bit when set make possible a freeze of the
MCPSM counter if the MIOB freeze line is activated. NOTE: This line is active when
MIOS14MCR[STOP] is set or when MIOS14MCR[FREN] and the IMB3 FREEZE line are set.
When the MCPSM is frozen, it stops counting. Then when the FREN bit is reset or when the
freeze condition on the MIOB is negated, the counter restarts from where it was before freeze.
The FREN bit is cleared by reset.
0 MCPSM counter not frozen.
1 MCPSM counter frozen if MIOB freeze active.
Reserved
Clock prescaler — This 4-bit read/write data register stores the modulus value for loading into
the clock prescaler. The new value is loaded into the counter on the next time the counter equals
one or when disabled (PREN =0).
Figure 17-9. MCPSM Status/Control Register (MCPSMSCR)
2
Hex
0xE
0xF
0x0
0x1
0x2
0x3
3
...
Table 17-7. MCPSMSCR Bit Descriptions
PSL[3:0] Value
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 17-8. Clock Prescaler Setting
4
5
0b0000
0b0001
0b0010
0b0011
0b1110
0b1111
Binary
...
0000_0000_0000_0000
6
NOTE
—
0x30 6816
7
No counter clock output
Description
8
Divide Ratio
9
16
14
15
...
2
3
10
11
12
Freescale Semiconductor
13
PSL3:0
14
LSB
15
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