UPD70F3453GC-8EA-A Renesas Electronics America, UPD70F3453GC-8EA-A Datasheet - Page 1025

• Manufacturer Part Number: UPD70F3453GC-8EA-A
• Description: MCU 32BIT 128KB FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3453GC-8EA-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

20.8 Interrupt Response Time of CPU
signals successively, input the next interrupt request signal at least 4 clocks after the preceding interrupt.
Instruction (start instruction of interrupt servicing routine)
Except the following cases, the interrupt response time of the CPU is 4 clocks minimum. To input interrupt request
• In IDLE/STOP mode
• When interrupt request non-sampling instructions are successively executed (see 20.9 Periods in Which CPU
• When an on-chip peripheral I/O register is accessed
Note For interleave accesses, refer to 8.1.2
Remark
Notes 1. V850E/IG3 only
Remark
Maximum
Minimum
Does Not Acknowledge Interrupts.)
(U14559E).
2. When LD instruction is executed to internal ROM (during align access)
3. For the number of internal system clocks, see 4.6 (1) Digital noise elimination 0 control register n
INT1 to INT4: Interrupt acknowledgment processing
IFX:
IDX:
(INTNFCn).
a = 02 to 07
Interrupt latency time (internal system clock)
Figure 20-14. Pipeline Operation at Interrupt Request Acknowledgment (Outline)
interrupt
Internal
7
Note 2
4
Interrupt acknowledgment operation
to INTP13, INTP17,
INTPa
INTP18, INTADT0,
CHAPTER 20 INTERRUPT/EXCEPTION PROCESSING FUNCTION
INTP00, INTP01,
Analog filter time
Analog filter time
Invalid instruction fetch
Invalid instruction decode
INTADT1
Note 1
4 +
7 +
, INTP08
External interrupt
Interrupt request
Internal clock
Instruction 1
Instruction 2
User’s Manual U18279EJ3V0UD
INTP14 to INTP16
Digital noise filter
Digital noise filter
4 + Note 3 +
7 + Note 3 +
2-clock branch in V850E1 Architecture User’s Manual
IF
The following cases are exceptions.
• In IDLE/STOP mode
• Access to external bus
• Two or more interrupt request non-sample
• Access to on-chip peripheral I/O register
instructions are executed in succession
IFX
IF
INT1 INT2 INT3 INT4
IFX
ID
4 system clocks
IDX
EX
Conditions
DF
WB
IF
Interleave access
IF
IF
ID
1023
Note