UPD70F3453GC-8EA-A Renesas Electronics America, UPD70F3453GC-8EA-A Datasheet - Page 1042
UPD70F3453GC-8EA-A
Manufacturer Part Number
UPD70F3453GC-8EA-A
Description
MCU 32BIT 128KB FLASH 100LQFP
Manufacturer
Renesas Electronics America
Series
V850E/Ix3r
Datasheet
1.UPD70F3451GC-UBT-A.pdf
(1191 pages)
Specifications of UPD70F3453GC-8EA-A
Core Processor
RISC
Core Size
32-Bit
Speed
64MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
56
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3.5 V ~ 5.5 V
Data Converters
A/D 10x12b, 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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(2) Reset operation (WDTRES) by overflow of watchdog timer (WDT)
(3) Reset operation (LVIRES) by low-voltage detector (LVI)
(4) Reset operation (POCRES) by power-on-clear circuit (POC)
If the reset mode is set to reset upon overflow of the watchdog timer (WDT) (WDTM.WDM1 and WDTM.WDM0
bits = 10 or 11), the system is reset and each hardware is initialized to a specific state when WDT overflows
(WDTRES).
If the WDTRES signal is generated, the RESF.WDTRF bit is set to 1, indicating that internal reset has
occurred.
The operations during the reset period and after release of reset, other than the operation of the RESF
register, are the same as the reset operation by RESET pin input (see (1) Reset operation by RESET pin
input).
When LVI operation is enabled, the supply voltage (V
if the supply voltage drops below the detection voltage, the system is reset (when the LVIM.LVIMD bit is set to
“1”) and each hardware is initialized to a specific state.
The system is reset when the supply voltage drops below the detection voltage and the reset is released when
the supply voltage is equal to or exceeds the detection voltage. After a reset is released, when the oscillation
stabilization time (default value of the OSTS register: 2
executing the program.
The status of each hardware during the reset period and after reset release is the same as the reset operation
by the RESET pin (see (1) Reset operation by RESET pin input).
For details of the reset operation by low-voltage detector (LVI), see CHAPTER 23
DETECTOR.
When the supply voltage (V
drops below the detection voltage (including at power application), the system is reset and each hardware is
initialized to a specific state.
The system is reset when the supply voltage drops below the detection voltage and the reset is released when
the supply voltage is equal to or exceeds the detection voltage. After a reset is released, when the oscillation
stabilization time (default value of the OSTS register: 2
executing the program.
The status of each hardware during the reset period and after reset release is the same as the reset operation
by the RESET pin (see (1) Reset operation by RESET pin input).
For details of the reset operation by power-on-clear circuit (POC), see CHAPTER 24 POWER-ON-CLEAR
CIRCUIT.
DD0
, V
CHAPTER 22 RESET FUNCTIONS
DD1
) and detection voltage (V
User’s Manual U18279EJ3V0UD
DD0
, V
14
14
/f
/f
DD1
X
X
) of the oscillator has elapsed, the CPU starts
) of the oscillator has elapsed, the CPU starts
) and detection voltage (V
POC0
) are compared and if the supply voltage
LVI
) are compared and
LOW-VOLTAGE
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