UPD70F3453GC-8EA-A Renesas Electronics America, UPD70F3453GC-8EA-A Datasheet - Page 811

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UPD70F3453GC-8EA-A

Manufacturer Part Number
UPD70F3453GC-8EA-A
Description
MCU 32BIT 128KB FLASH 100LQFP
Manufacturer
Renesas Electronics America
Series
V850E/Ix3r
Datasheet

Specifications of UPD70F3453GC-8EA-A

Core Processor
RISC
Core Size
32-Bit
Speed
64MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
56
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3.5 V ~ 5.5 V
Data Converters
A/D 10x12b, 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD70F3453GC-8EA-A
Manufacturer:
Renesas Electronics America
Quantity:
10 000
16.2 Features
Remark
• Reception end interrupt request signal (INTCBnR):
• Transmission enable interrupt request signal (INTCBnT): This signal is generated when transmission is
• Reception error interrupt request signal (INTCBnRE):
Transfer rate: 8 Mbps (using internal clock)
Master mode and slave mode selectable
Interrupt request signals: 3
Serial clock and data phase switchable
3-wire serial interface, transfer data length selectable in 1-bit units between 8 and 16 bits
Transfer data MSB-first/LSB-first switchable
3-wire transfer SOBn:
Double buffer for both transmission and reception
Overrun error detection
Transmission mode, reception mode, and transmission/reception mode specifiable
n = 0 to 2
SIBn:
SCKBn: Serial clock I/O
CHAPTER 16 CLOCKED SERIAL INTERFACE B (CSIB)
Serial data output
Serial data input
User’s Manual U18279EJ3V0UD
This signal is generated when reception is enabled
and receive data is transferred from the shift register
to the CSIBn receive data register (CBnRX) after
completion of a serial transfer.
enabled
continuous
transmission data is transferred from the CSIBn
transmit data register (CBnTX) to the shift register.
(CBnSTR.CBnOVE bit = 1) when reception is
enabled in the continuous transfer mode.
This signal is generated if an overrun error occurs
in
transmission/reception
the
continuous
transmission
mode
809
and
or

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