UPD70F3453GC-8EA-A Renesas Electronics America, UPD70F3453GC-8EA-A Datasheet - Page 725

• Manufacturer Part Number: UPD70F3453GC-8EA-A
• Description: MCU 32BIT 128KB FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3453GC-8EA-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

14.4 Control Registers
(1) UARTAn control register 0 (UAnCTL0)
The UAnCTL0 register is an 8-bit register that controls the UARTAn serial transfer operation.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 10H.
(n = 0 to 2)
UAnCTL0
After reset: 10H
CHAPTER 14 ASYNCHRONOUS SERIAL INTERFACE A (UARTA)
UAnPWR
UAnPWR
The UARTAn operation is controlled by the UAnPWR bit. The TXDAn pin output
is fixed to high level by clearing the UAnPWR bit to 0 (fixed to low level if
UAnOPT0.UAnTDL bit = 1).
UAnTXE
• To start transmission, set the UAnPWR bit to 1 and then set the UAnTXE bit to 1.
• To initialize the transmission unit, clear the UAnTXE bit to 0, wait for two cycles of
• When the operation is enabled (UAnPWR bit = 1), the transmission operation is
• When the UAnPWR bit is cleared to 0, the status of the internal circuit becomes
UAnRXE
• To start reception, set the UAnPWR bit to 1 and then set the UAnRXE bit to 1.
• To initialize the reception unit, clear the UAnRXE bit to 0, wait for two cycles of
• When the operation is enabled (UAnPWR bit = 1), the reception operation is
• When the UAnPWR bit is cleared to 0, the status of the internal circuit becomes
the base clock (f
initialization may not be executed (for the base clock, see 14.7 (1) (a) Base clock).
enabled after two or more cycles of the base clock (f
UAnTXE = 1.
the same status as UAnTXE bit = 0 by the UAnPWR bit even if the UAnTXE bit is
1. The transmission operation is enabled when the UAnPWR bit is set to 1 again.
the base clock, and then set the UAnRXE bit to 1 again. Otherwise, initialization
may not be executed (for the base clock, see 14.7 (1) (a) Base clock).
enabled after two or more cycles of the base clock (f
UAnRXE = 1. The start bit is ignored if it is received before the reception operation
is enabled.
the same status as UAnRXE bit = 0 by the UAnPWR bit even if the UAnRXE bit is
1. The reception operation is enabled when the UAnPWR bit is set to 1 again.
<7>
0
1
0
1
0
1
Disable UARTAn operation (UARTAn reset asynchronously)
Enable UARTAn operation
Disable transmission operation
Enable transmission operation
Disable reception operation
Enable reception operation
R/W
UAnTXE UAnRXE UAnDIR
<6>
UCLK
Address: UA0CTL0 FFFFFA00H, UA1CTL0 FFFFFA10H,
User’s Manual U18279EJ3V0UD
), and then set the UAnTXE bit to 1 again. Otherwise,
<5>
UA2CTL0 FFFFFA20H
Transmission operation enable
Reception operation enable
UARTAn operation control
<4>
UAnPS1 UAnPS0
3
UCLK
UCLK
2
) have elapsed since
) have elapsed since
UAnCL
1
UAnSL
0
(1/2)
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