UPD70F3453GC-8EA-A Renesas Electronics America, UPD70F3453GC-8EA-A Datasheet - Page 18

• Manufacturer Part Number: UPD70F3453GC-8EA-A
• Description: MCU 32BIT 128KB FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3453GC-8EA-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

CHAPTER 20 INTERRUPT/EXCEPTION PROCESSING FUNCTION............................................... 983
16
19.4 Transfer Modes....................................................................................................................... 973
19.5 Transfer Types........................................................................................................................ 977
19.6 Transfer Target ....................................................................................................................... 977
19.7 DMA Channel Priorities ......................................................................................................... 977
19.8 Next Address Setting Function............................................................................................. 978
19.9 DMA Transfer Start Factors .................................................................................................. 979
19.10 Forcible Termination.............................................................................................................. 980
19.11 Times Related to DMA Transfer............................................................................................ 981
19.12 Cautions .................................................................................................................................. 981
19.13 DMA Transfer End .................................................................................................................. 982
20.1 Features .................................................................................................................................. 983
20.2 Non-Maskable Interrupts ....................................................................................................... 988
20.3 Maskable Interrupts ............................................................................................................... 993
20.4 External Interrupt Request Input Pins (INTP00 to INTP18, INTADT0, INTADT1) ........... 1010
20.5 Software Exception .............................................................................................................. 1015
20.6 Exception Trap ..................................................................................................................... 1017
20.7 Multiple Interrupt Servicing Control................................................................................... 1021
20.8 Interrupt Response Time of CPU........................................................................................ 1023
19.3.1
19.3.2
19.3.3
19.3.4
19.3.5
19.3.6
19.4.1
19.4.2
19.4.3
19.5.1
19.6.1
20.2.1
20.2.2
20.2.3
20.3.1
20.3.2
20.3.3
20.3.4
20.3.5
20.3.6
20.3.7
20.4.1
20.4.2
20.5.1
20.5.2
20.5.3
20.6.1
20.6.2
DMA source address registers 0 to 3 (DSA0 to DSA3)..............................................................961
DMA destination address registers 0 to 3 (DDA0 to DDA3).......................................................963
DMA transfer count registers 0 to 3 (DBC0 to DBC3)................................................................965
DMA addressing control registers 0 to 3 (DADC0 to DADC3) ...................................................966
DMA channel control registers 0 to 3 (DCHC0 to DCHC3)........................................................967
DMA trigger factor registers 0 to 3 (DTFR0 to DTFR3) .............................................................969
Single transfer mode .................................................................................................................973
Single-step transfer mode..........................................................................................................975
Block transfer mode...................................................................................................................976
2-cycle transfer ..........................................................................................................................977
Transfer type and transfer target ...............................................................................................977
Operation...................................................................................................................................989
Restore ......................................................................................................................................991
Non-maskable interrupt status flag (NP)....................................................................................992
Operation...................................................................................................................................993
Restore ......................................................................................................................................995
Priorities of maskable interrupts ................................................................................................996
Interrupt control registers (xxICn) ............................................................................................1000
Interrupt mask registers 0 to 5 (IMR0 to IMR5)........................................................................1005
In-service priority register (ISPR).............................................................................................1008
Maskable interrupt status flag (ID)...........................................................................................1009
Noise elimination .....................................................................................................................1010
Edge detection.........................................................................................................................1010
Operation.................................................................................................................................1015
Restore ....................................................................................................................................1016
Exception status flag (EP) .......................................................................................................1017
Illegal opcode definition ...........................................................................................................1017
Debug trap...............................................................................................................................1019
User’s Manual U18279EJ3V0UD