UPD70F3453GC-8EA-A Renesas Electronics America, UPD70F3453GC-8EA-A Datasheet - Page 859

• Manufacturer Part Number: UPD70F3453GC-8EA-A
• Description: MCU 32BIT 128KB FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3453GC-8EA-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

17.3 Configuration
I
(1) IIC shift register 0 (IIC0)
(2) Slave address register 0 (SVA0)
(3) SO latch
(4) Wakeup controller
(5) Prescaler
(6) Serial clock counter
(7) Interrupt request signal generator
2
C includes the following hardware.
The IIC0 register is used to convert 8-bit serial data to 8-bit parallel data and to convert 8-bit parallel data to 8-
bit serial data. The IIC0 register can be used for both transmission and reception.
Write and read operations to the IIC0 register are used to control the actual transmit and receive operations.
The IIC0 register can be read or written in 8-bit units.
Reset sets IIC0 to 00H.
The SVA0 register sets local addresses when in slave mode.
The SVA0 register can be read or written in 8-bit units.
Reset sets SVA0 to 00H.
The SO latch is used to retain the SDA pin’s output level.
This circuit generates an interrupt request signal (INTIIC) when the address received by this register matches
the address value set to the SVA0 register or when an extension code is received.
This selects the sampling clock to be used.
This counter counts the serial clocks that are output and the serial clocks that are input during transmit/receive
operations and is used to verify that 8-bit data was sent or received.
This circuit controls the generation of interrupt request signals (INTIIC).
An I
• Falling of the eighth or ninth clock of the serial clock (set by IICC0.WTIM0 bit)
• Interrupt request generated when a stop condition is detected (set by IICC0.SPIE0 bit)
2
C interrupt is generated following either of two triggers.
Registers
Control registers
Item
Table 17-1. Configuration of I
User’s Manual U18279EJ3V0UD
CHAPTER 17 I
IIC shift register 0 (IIC0)
Slave address register 0 (SVA0)
IIC control register 0 (IICC0)
IIC status register 0 (IICS0)
IIC flag register 0 (IICF0)
IIC clock select register 0 (IICCL0)
IIC function expansion register 0 (IICX0)
IICOPS clock select register (IICOCKS)
2
C BUS
Configuration
2
C
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