UPD70F3453GC-8EA-A Renesas Electronics America, UPD70F3453GC-8EA-A Datasheet - Page 173
UPD70F3453GC-8EA-A
Manufacturer Part Number
UPD70F3453GC-8EA-A
Description
MCU 32BIT 128KB FLASH 100LQFP
Manufacturer
Renesas Electronics America
Series
V850E/Ix3r
Datasheet
1.UPD70F3451GC-UBT-A.pdf
(1191 pages)
Specifications of UPD70F3453GC-8EA-A
Core Processor
RISC
Core Size
32-Bit
Speed
64MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
56
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3.5 V ~ 5.5 V
Data Converters
A/D 10x12b, 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3453GC-8EA-A
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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(3) Digital noise elimination 2 control register n (TTNFCn)
Note V850E/IG3 only
The TTNFCn register is used to select the sampling clock that is used to eliminate digital noise on the TITn0,
TITn1, EVTTn, TENCn0, TENCn1, or TECRn pin. If the same level is not detected on these pins three times
in sequence using the clock selected by the TTNFCn register, the signal is eliminated as noise.
This register can be read or written in 8-bit units.
Reset sets this register to 00H.
Cautions 1. If the input signal lasts for the duration of 2 or 3 clocks, it is undefined whether the signal
V850E/IF3
V850E/IG3
TTNFCn
n = 1
n = 0, 1
2. If noise is generated in synchronization with the sampling clock, eliminate the noise by
3. Noise is not eliminated if the pin is used as a normal input port pin.
4. The noise elimination function starts operating when the TTnCTL0.TTnCE bit is set to 1
After reset: 00H
is detected as a valid edge or eliminated as noise. So that the signal is actually detected
as a valid edge, the same signal level must be input for a duration of 3 clocks or more.
attaching a filter to the input pin.
(enabling count operations).
TTNFENn
TTNFENn
TTNFCn2
0
0
0
0
1
1
0
1
7
Other than above
TTNFCn1
Disables digital noise elimination
Enables digital noise elimination
R/W
0
0
1
1
0
0
6
0
CHAPTER 4 PORT FUNCTIONS
User’s Manual U18279EJ3V0UD
Address: TTNFC0 FFFFF5A0H
TTNFCn0
0
1
0
1
0
1
5
0
Setting of digital noise elimination
f
f
f
f
f
f
Setting prohibited
XX
XX
XX
XX
XX
XX
/4
/8
/16
/32
/64
4
0
Sampling clock selection
3
0
Note
TTNFCn2 TTNFCn1 TTNFCn0
, TTNFC1 FFFFF5A2H
2
1
0
171
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