UPD70F3453GC-8EA-A Renesas Electronics America, UPD70F3453GC-8EA-A Datasheet - Page 397

• Manufacturer Part Number: UPD70F3453GC-8EA-A
• Description: MCU 32BIT 128KB FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3453GC-8EA-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(e) Clearing overflow flag
Note The overflow counter is set arbitrarily by software on the internal RAM.
<1> Read the TABnCCRa register (setting of the default value of the TIBna pin input).
<2> An overflow occurs. Increment the overflow counter and clear the overflow flag to 0 in the overflow
<3> An overflow occurs a second time. Increment (+1) the overflow counter and clear the overflow flag
<4> Read the TABnCCRa register.
Remark
The overflow flag can be cleared to 0 by clearing the TABnOVF bit to 0 with the CLR instruction after
reading the TABnOVF bit when it is 1 and by writing 8-bit data (bit 0 is 0) to the TABnOPT0 register after
reading the TABnOVF bit when it is 1.
TABnCCRa register
INTTBnOV signal
interrupt servicing.
to 0 in the overflow interrupt servicing.
Read the overflow counter.
→ When the overflow counter is “N”, the pulse width can be calculated by (N × 10000H + D
Clear the overflow counter (0H).
TIBna pin input
16-bit counter
D
In this example, the pulse width is (20000H + D
TABnOVF bit
a0
TABnCE bit
n = 0, 1
a = 0 to 3
counter
).
Overflow
FFFFH
0000H
Note
CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB)
Example when capture trigger interval is long
User’s Manual U18279EJ3V0UD
0H
D
a0
<1> <2>
a1
1 cycle of 16-bit counter
– D
a0
Pulse width
) because an overflow occurs twice.
D
1H
a0
<3> <4>
D
a1
2H 0H
D
a1
a1
–
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