UPD70F3453GC-8EA-A Renesas Electronics America, UPD70F3453GC-8EA-A Datasheet - Page 682

• Manufacturer Part Number: UPD70F3453GC-8EA-A
• Description: MCU 32BIT 128KB FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3453GC-8EA-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

12.6 Cautions
12.6.1 Stopping conversion operation
conversion result in the A/Dn conversion result register m (ADnCRm) and A/Dn conversion result extension register a
(ADnECRa) is undefined. Therefore, read the A/D conversion result after A/D conversion has been completed (after
the A/Dn conversion end interrupt request signal (INTADn) has been issued), and then write 0 to the ADnCE bit as
necessary.
12.6.2 Interval of trigger during conversion operation in hardware trigger mode, conversion channel
specification mode, and extension buffer mode. Therefore, the interval of the trigger (input time) in the hardware
trigger mode, conversion channel specification mode, and extension buffer mode must be longer than the A/D
conversion time specified by the ADnCTC.ADnFR3 to ADnCTC.ADnFR0 bits (see Table 12-2 Number of A/D
Conversion Clocks and A/D Conversion Time).
12.6.3 Writing to ADnSCM register
12.6.4 A/D conversion start timing
1.5 basic clocks (f
680
The ongoing conversion operation is stopped when 0 is written to the ADnSCM.ADnCE bit. At this time, the
Note that the ADnCE bit is not cleared to 0 in all the modes even after the INTADn signal is generated.
Remark
Inputting a trigger during conversion operation is ignored in the hardware trigger mode, conversion channel
Remark
(1) Restarting A/D conversion
(2) Contention between end of A/D conversion and writing to ADnSCM register
(3) Successive writing to ADnSCM register
In the conversion channel specification mode and extension buffer mode, starting A/D conversion is delayed up to
Remark
To restart A/D conversion, write the same value to the ADnSCM register. To change the ADnPLM, ADnTRG1,
and ADnTRG0 bits, be sure to set the ADnCE bit to 0.
If completion of A/D conversion contends with writing to the ADnSCM register during A/D conversion operation,
the conversion result is correctly stored in the ADnCRm and ADnECRa registers, if the A/Dn conversion end
interrupt request signal (INTADn) is generated. If the INTADn signal is not generated, the A/D conversion
operation is aborted.
registers.
To successively write the ADnSCM register when the conversion operation is enabled (ADnCE bit = 1), be
sure to wait for time of at least 5 basic clocks (f
The ADnSCM register can be successively written when the ADnCE bit is set to 1 after the ADnSCM register is
written while the ADnCE bit = 0.
specification mode, and extension buffer mode
n = 0, 1
m = 0 to 15
n = 0, 1
n = 0, 1
AD01
) as compared with the normal operation mode.
Therefore, the previous conversion result is held by the ADnCRm and ADnECRa
CHAPTER 12 A/D CONVERTERS 0 AND 1
User’s Manual U18279EJ3V0UD
AD01
).