UPD70F3453GC-8EA-A Renesas Electronics America, UPD70F3453GC-8EA-A Datasheet - Page 1033
UPD70F3453GC-8EA-A
Manufacturer Part Number
UPD70F3453GC-8EA-A
Description
MCU 32BIT 128KB FLASH 100LQFP
Manufacturer
Renesas Electronics America
Series
V850E/Ix3r
Datasheet
1.UPD70F3451GC-UBT-A.pdf
(1191 pages)
Specifications of UPD70F3453GC-8EA-A
Core Processor
RISC
Core Size
32-Bit
Speed
64MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
56
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3.5 V ~ 5.5 V
Data Converters
A/D 10x12b, 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Company:
Part Number:
UPD70F3453GC-8EA-A
Manufacturer:
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21.4 IDLE Mode
21.4.1 Setting and operation status
mode.
peripheral functions stops.
retained. The CPU and other on-chip peripheral functions stop operating. However, the on-chip peripheral functions
that can operate with an external clock continue operating.
the on-chip peripheral functions. The clock generator and PLL do not stop, so the normal operation mode can be
restored without waiting for the oscillation stabilization time after the IDLE mode has been released, in the same
manner as when the HALT mode is released.
21.4.2 Releasing IDLE mode
(V850E/IG3 only), INTP08 to INTP13, INTP17, INTP18, INTADT0, or INTADT1 pin input), an unmasked internal
interrupt request signal (CSIB-related interrupt request signal in the slave mode) from the peripheral functions
operable in the IDLE mode, or a reset signal (RESET pin input, reset signal (LVIRES) generation by low-voltage
detector (LVI), or reset signal (POCRES) generation by power-on-clear circuit (POC)).
The IDLE mode is set by clearing (0) the PSMR.PSM0 bit and setting (1) the PSC.STB bit in the normal operation
In the IDLE mode, the clock generator and PLL continue operation but clock supply to the CPU and other on-chip
As a result, program execution stops and the contents of the internal RAM before the IDLE mode was set are
Table 21-5 shows the operation status in the IDLE mode.
The IDLE mode can reduce the power consumption more than the HALT mode because it stops the operation of
Caution Insert five or more NOP instructions after the instruction that stores data in the PSC register to
The IDLE mode is released by an unmasked external interrupt request signal (INTP00, INTP01, INTP02 to INTP07
After the IDLE mode has been released, the normal operation mode is restored.
(1) Releasing IDLE mode by unmasked maskable interrupt request signal
The IDLE mode is released by an unmasked maskable interrupt request signal, regardless of the priority of the
interrupt request. If the IDLE mode is set in an interrupt servicing routine, however, an interrupt request that is
issued later is processed as follows.
Caution When PSC.INTM bit = 1, the IDLE mode cannot be released by the unmasked maskable
(a) If an interrupt request with a priority lower than or same as the interrupt request signal currently being
(b) If an interrupt request signal with a priority higher than that of the interrupt request signal currently being
serviced is generated, the IDLE mode is released, but the newly generated interrupt is not acknowledged.
The interrupt request signal itself is retained. Therefore, execution starts at the next instruction after the
IDLE instruction.
serviced is issued (including a non-maskable interrupt request signal), the IDLE mode is released and that
interrupt request signal is acknowledged. Therefore, execution branches to the handler address.
set the IDLE mode.
interrupt request signal.
CHAPTER 21 STANDBY FUNCTION
User’s Manual U18279EJ3V0UD
1031
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