UPD70F3453GC-8EA-A Renesas Electronics America, UPD70F3453GC-8EA-A Datasheet - Page 736

• Manufacturer Part Number: UPD70F3453GC-8EA-A
• Description: MCU 32BIT 128KB FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3453GC-8EA-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

14.6.4 UART reception
bit to 1. In the reception wait status, the RXDAn pin is monitored and start bit detection is performed.
recognized if the RXDAn pin is low level at the start bit sampling point. After a start bit has been recognized, the
receive operation starts, and serial data is saved to the UARTAn receive shift register according to the set baud rate.
UARTAn receive shift register is written to the UAnRX register. However, if an overrun error occurs (UAnSTR.UAnOVE
bit = 1), the receive data at this time is not written to the UAnRX register and is discarded.
reception continues until the reception position of the first stop bit, and the INTUAnRE signal is output following
reception end.
734
The reception wait status is set by setting the UAnCTL0.UAnPWR bit to 1 and then setting the UAnCTL0.UAnRXE
Start bit detection is performed using a two-step detection routine.
First the falling edge of the RXDAn pin is detected and sampling is started at the falling edge. The start bit is
When the reception end interrupt request signal (INTUAnR) is output upon reception of the stop bit, the data of the
Even if a parity error (UAnSTR.UAnPE bit = 1) or a framing error (UAnSTR.UAnFE bit = 1) occurs during reception,
Remark
Cautions 1. Be sure to read the UAnRX register even when a reception error occurs. If the UAnRX register
Remark
INTUAnR signal
UAnRX register
2. The operation during reception is performed assuming that there is only one stop bit. A
3. When reception is completed, read the UAnRX register after the reception end interrupt
4. If receive end processing (INTUAnR signal generation) of UARTAn and the UAnPWR bit = 0 or
n = 0 to 2
▽: Start bit sampling point
is not read, an overrun error occurs during reception of the next data, and reception errors
continue occurring indefinitely.
second stop bit is ignored.
request signal (INTUAnR) has been generated, and clear the UAnPWR or UAnRXE bit to 0. If
the UAnPWR or UAnRXE bit is cleared to 0 before the INTUAnR signal is generated, the read
value of the UAnRX register cannot be guaranteed.
UAnRXE bit = 0 conflict, the INTUAnR signal may be generated in spite of these being no data
stored in the UAnRX register. To end reception without waiting INTUAnR signal generation,
be sure to clear (0) the interrupt request flag (UAnRIC.UAnRIF), after setting (1) the interrupt
mask flag (UAnRIC.UAnRMK) and then set (1) the UAnPWR bit = 0 or UAnRXE bit = 0.
CHAPTER 14 ASYNCHRONOUS SERIAL INTERFACE A (UARTA)
Start
bit
D0
Figure 14-9. UART Reception
User’s Manual U18279EJ3V0UD
D1
D2
D3
D4
D5
D6
D7
Parity
bit
Stop
bit