UPD70F3453GC-8EA-A Renesas Electronics America, UPD70F3453GC-8EA-A Datasheet - Page 761

• Manufacturer Part Number: UPD70F3453GC-8EA-A
• Description: MCU 32BIT 128KB FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3453GC-8EA-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(5) UARTB receive data register AP (UBRXAP), UARTB receive data register (UBRX)
These registers store parallel data converted by the receive shift register. They function as the 8-bit × 1-
stage UBRX register, in the single mode (UBFIC0.UBMOD bit = 0), and as the 16-bit × 16-stage receive FIFO
(UBRXAP register) in the FIFO mode (UBFIC0.UBMOD bit = 1).
The receive data is stored in the lower 8 bits of the receive FIFO (UBRXAP register) and the error information
of the received data is stored in the higher 8 bits (bit 8 and bit 9). If a reception error (such as a parity error or
a framing error) occurs in the FIFO mode, the UBRXAP register is read in 16-bit (halfword) units. In this way,
the flag of the data stored in receive FIFO can be checked (error information is appended as UBPEF bit = 1
or UBFEF bit = 1), so that the error data can be recognized (when the lower 8 bits of the UBRXAP register
are read in 8-bit (byte) units, the higher 8 bits are discarded. Therefore, if no error has occurred, the receive
data of the UBRXAP register can be read successively by being read in 8-bit (byte) units in the same way as
the UBRX register).
If reception is enabled (UBCTL0.UBRXE bit = 1), the receive data is transferred from the receive shift register
to the receive data register, in synchronization with the completion of the shift-in processing of one frame.
By transferring the receive data to the UBRX register in the single mode or by transferring the number of
receive data set as the trigger by the UBFIC2.UBRT3 to UBFIC2.UBRT0 bits to the receive FIFO in the FIFO
mode, a reception end interrupt request signal (INTUBTIR) is generated. If data is stored in receive FIFO
when the next data does not come (start bit is not detected) even after the next data reception wait time
specified by the UBFIC1.UBTC4 to UBFIC1.UBTC0 bits has elapsed in the FIFO mode, a reception timeout
interrupt request signal (INTUBTITO) is generated.
For information about the timing for generating these interrupt requests, see 15.5
Signals.
If data is received with the LSB first when the data length is specified as 7 bits, the received data is
transferred to bits 6 to 0 of the receive data register from the LSB (bit 0), with the MSB (bit 7) always being 0.
If data is received with the MSB first, it is transferred to bits 7 to 1 of the receive data register from the MSB
(bit 7) with the LSB (bit 0) always being 0. However, if an overrun error occurs, the receive data at that time
is not transferred to the receive data register.
The UBRXAP register is read-only in 16-bit units. However, the lower 8 bits of the UBRXAP register are
read-only in 8-bit units.
The UBRX register is read-only in 8-bit units.
In addition to reset input, the value of these registers can be set to FFH in the single mode or to 00FFH in the
FIFO mode, by clearing the UBCTL0.UBPWR bit to 0.
Cautions 1. The UBPEF and UBFEF bits cannot be read because these registers serve as 8-bit
2. When no reception error has occurred in the FIFO mode, the receive data of the
registers in the single mode.
UBRXAP register can be read successively by reading the lower 8 bits of the UBRXAP
register in 8-bit (byte) units. An 8-bit access to the higher 8 bits is prohibited. If they
are accessed, the operation is not guaranteed.
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE B (UARTB)
User’s Manual U18279EJ3V0UD
Interrupt Request
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