UPD70F3453GC-8EA-A Renesas Electronics America, UPD70F3453GC-8EA-A Datasheet - Page 778

• Manufacturer Part Number: UPD70F3453GC-8EA-A
• Description: MCU 32BIT 128KB FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3453GC-8EA-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

15.7.2 Transmit operation
transmission is started when transmit data is written to the UBTX register.
as the trigger by the UBFIC2.UBTT3 to UBFIC2.UBTT0 bits and 16 bytes or less is written to transmit FIFO and then
the UBTXE bit is set to 1.
776
In the single mode (UBFIC0.UBMOD bit = 0), transmission is enabled when the UBCTL0.UBTXE bit is set to 1, and
In the FIFO mode (UBFIC0.UBMOD bit = 1), transmission is started when transmit data of at least the number set
Caution Setting the UBCTL0.UBTXE bit to 1 before writing transmit data to transmit FIFO in the FIFO
(1) Transmission enabled state
(2) Starting a transmit operation
This state is set by the UBCTL0.UBTXE bit.
• UBTXE = 1: Transmission enabled state
• UBTXE = 0: Transmission disabled state
However, because this bit is also used by CSIB2, enable transmission after setting the CB2CTL0.CB2PWR
bit to 0.
Since UARTB does not have a CTS (transmission enabled signal) input pin, a port should be used to confirm
whether the destination is in the reception enabled state.
• In single mode (UBFIC0.UBMOD bit = 0)
• In FIFO mode (UBFIC0.UBMOD bit = 1)
Data in the transmit data register (UBTX register in single mode or transmit FIFO in the FIFO mode) is
transferred to the transmit shift register when transmission is started. Then, the transmit shift register outputs
data to the TXDB pin sequentially beginning with the LSB (the transmit data is transferred sequentially
starting with the start bit). The start bit, parity bit, and stop bits are added automatically.
In the single mode, transmission is started when transmit data is written to the UBTX register while
transmission is enabled.
In the FIFO mode, transmission is started when transmit data of at least the number set as the trigger by
the UBFIC2.UBTT3 to UBFIC2.UBTT0 bits and 16 bytes or less is written to transmit FIFO and then
transmission is enabled (UBTXE bit = 1).
mode is prohibited. The operation is not guaranteed if this setting is made.
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE B (UARTB)
User’s Manual U18279EJ3V0UD