UPD70F3453GC-8EA-A Renesas Electronics America, UPD70F3453GC-8EA-A Datasheet - Page 862

• Manufacturer Part Number: UPD70F3453GC-8EA-A
• Description: MCU 32BIT 128KB FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3453GC-8EA-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

860
After reset: 00H
LREL0
(1) IIC control register 0 (IICC0)
Notes 1.
Caution If the I
Be sure to set this bit to 1 when the SCL and SDA lines are high level.
Condition for clearing (IICE0 bit = 0)
• Cleared by instruction
• Reset
The standby mode following exit from communications remains in effect until the following communications entry conditions
are met.
• After a stop condition is detected, restart is in master mode.
• An address match or extension code reception occurs after the start condition.
Condition for clearing (LREL0 bit = 0)
• Automatically cleared after execution
• Reset
IICC0
0
1
IICE0
The IICC0 register is used to enable/stop I
The IICC0 register can be read or written in 8-bit or 1-bit units. However, set the SPIE0, WTIM0, and ACKE0
bits when the IICE0 bit is 0 or during the wait period. When setting the IICE0 bit from “0” to “1”, these bits can
also be set at the same time.
Reset sets this register to 00H.
Note 2
0
1
2.
Normal operation
This exits from the current communications and sets standby mode. This setting is automatically cleared to 0 after
being executed.
Its uses include cases in which a locally irrelevant extension code has been received.
The SCL and SDA lines are set to high impedance.
The STT0, SPT0, IICS0.MSTS0, IICS0.EXC0, IICS0.COI0, IICS0.TRC0, IICS0.ACKD0, and IICS0.STD0 bits are
cleared to 0.
is low level, the start condition is detected immediately. To avoid this, after enabling the I
operation, immediately set the LREL0 bit to 1 with a bit manipulation instruction.
IICE0
The IICS0 register, and the IICF0.STCF0, IICF0.IICBSY0, IICCL0.CLD0, and IICCL0.DAD0 bits are
reset.
This flag’s signal is invalid when the IICE0 bit = 0.
<7>
Stop operation. Reset the IICS0 register
Enable operation.
2
C operation is enabled (IICE0 bit = 1) when the SCL line is high level and the SDA line
R/W
LREL0
<6>
Address: FFFFFD82H
WREL0
<5>
User’s Manual U18279EJ3V0UD
SPIE0
CHAPTER 17 I
I
2
<4>
C operation enable/disable specification
2
C operations, set wait timing, and set other I
Exit from communications
Note 1
. Stop internal operation.
WTIM0
<3>
Condition for setting (LREL0 bit = 1)
• Set by instruction
Condition for setting (IICE0 bit = 1)
• Set by instruction
2
C BUS
ACKE0
<2>
STT0
<1>
SPT0
<0>
2
C operations.
2
C
(1/4)