UPD70F3453GC-8EA-A Renesas Electronics America, UPD70F3453GC-8EA-A Datasheet - Page 968

• Manufacturer Part Number: UPD70F3453GC-8EA-A
• Description: MCU 32BIT 128KB FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3453GC-8EA-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

19.3.4 DMA addressing control registers 0 to 3 (DADC0 to DADC3)
to 3). These registers cannot be accessed during a DMA operation.
966
The DADC0 to DADC3 registers are 16-bit registers that control the DMA transfer mode for DMA channel n (n = 0
These registers can be read or written in 16-bit units.
Reset sets these registers to 0000H.
Cautions 1. The DSn0 bit sets how many bits of data are to be transferred.
Caution Be sure to set bits 15, 13 to 8, 1, and 0 to “0”. If they are set to “1”, the operation is not
2. Set the DADCn register when the target channel is in one of the following periods (the
If the transfer data size is set to 16 bits, transfer is always started from an address with the
lowest bit of the address aligned to “0”. In this case, transfer cannot be started from an odd
address.
operation is not guaranteed if the register is set at any other time).
• Period from system reset to the generation of the first DMA transfer request
• Period from end of DMA transfer (after terminal count) to the generation of the next DMA
• Period from forced termination of DMA transfer (after the DCHCn.INITn bit was set to 1) to
guaranteed.
transfer request
the generation of the next DMA transfer request
(n = 0 to 3)
DADCn
After reset:
SADn1
DADn1
SADn1
CHAPTER 19 DMA FUNCTIONS (DMA CONTROLLER)
DSn0
TMn1
0000H
15
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
7
SADn0
SADn0
DADn0
8 bits
16 bits
DSn0
TMn0
R/W
14
6
0
1
0
1
0
1
0
1
0
1
0
1
User’s Manual U18279EJ3V0UD
Setting of count direction of transfer destination address for DMA channel n
Address: DADC0 FFFFF0D0H, DADC1 FFFFF0D2H,
Setting of count direction of transfer source address for DMA channel n
DADn1
Increment
Decrement
Fixed
Setting prohibited
Increment
Decrement
Fixed
Setting prohibited
Single transfer mode
Single-step transfer mode
Setting prohibited
Block transfer mode
13
Setting of transfer data size for DMA transfer
0
5
Setting of transfer mode during DMA transfer
DADC2 FFFFF0D4H, DADC3 FFFFF0D6H
DADn0
12
0
4
TMn1
11
0
3
TMn0
10
0
2
9
0
1
0
0
0
8
0