UPD70F3453GC-8EA-A Renesas Electronics America, UPD70F3453GC-8EA-A Datasheet - Page 843

• Manufacturer Part Number: UPD70F3453GC-8EA-A
• Description: MCU 32BIT 128KB FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3453GC-8EA-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(2) Operation timing
Caution In continuous transmission mode, the reception end interrupt request signal (INTCBnR) is not
Remark
INTCBnT signal
CBnTSF bit
SCKBn pin
SOBn pin
(1) Write 07H to the CBnCTL1 register, and select communication type 1, communication clock (f
(2) Write 00H to the CBnCTL2 register, and set the transfer data length to 8 bits.
(3) Write C3H to the CBnCTL0 register, and select the transmission mode, MSB first, and continuous
(4) The CBnSTR.CBnTSF bit is set to 1 by writing the transmit data to the CBnTX register, and the device
(5) When a serial clock is input, output the transmit data from the SOBn pin in synchronization with the
(6) When transfer of the transmit data from the CBnTX register to the shift register is ended and writing to
(7) To continue transmission, write the transmit data to the CBnTX register again after the INTCBnT signal
(8) When a serial clock is input following end of the transmission of the transfer data length set with the
(9) When transfer of the transmit data from the CBnTX register to the shift register is ended and writing to
(10) When the clock of the transfer data length set with the CBnCTL2 register is input without writing to the
(11) To release the transmission enable status, write the CBnCTL0.CBnPWR bit = 0 and the
external clock (SCKBn), and slave mode.
transfer mode at the same time as enabling the operation of the communication clock (f
waits for a serial clock input.
serial clock.
the CBnTX register is enabled, the transmission enable interrupt request signal (INTCBnT) is
generated.
is generated.
CBnCTL2 register, continuous transmission is started.
the CBnTX register is enabled, the INTCBnT signal is generated. To end continuous transmission at
the current transmission, do not write to the CBnTX register.
CBnTX register, clear the CBnTSF bit to 0 to end transmission.
CBnCTL0.CBnTXE bit = 0 after checking that the CBnTSF bit = 0.
generated.
n = 0 to 2
(1)
(2)
(3)
(4)
(5)
Bit 7
(6)
Bit 6
CHAPTER 16 CLOCKED SERIAL INTERFACE B (CSIB)
Bit 5
Bit 4 Bit 3
(7)
User’s Manual U18279EJ3V0UD
Bit 2
Bit 1
Bit 0
(8)
Bit 7
(9)
Bit 6
Bit 5
Bit 4 Bit 3
Bit 2
Bit 1
(10)
Bit 0
CCLK
(11)
).
CCLK
) =
841