UPD70F3453GC-8EA-A Renesas Electronics America, UPD70F3453GC-8EA-A Datasheet - Page 907

• Manufacturer Part Number: UPD70F3453GC-8EA-A
• Description: MCU 32BIT 128KB FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3453GC-8EA-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

17.9 Address Match Detection Method
slave address.
a local address has been set to the SVA0 register and when the address set to the SVA0 register matches the slave
address sent by the master device, or when an extension code has been received.
17.10
the transmitting device, so the IIC0 register data prior to transmission can be compared with the transmitted IIC0
register data to enable detection of transmission errors. A transmission error is judged as having occurred when the
compared data values do not match.
17.11
When in I
Address match detection is performed automatically by hardware. An INTIIC interrupt request signal occurs when
In I
(1) When the higher 4 bits of the receive address are either 0000 or 1111, the extension code flag (EXC0) is set
(2) If 11110xx0 is set to the SVA0 register by a 10-bit address transfer and 11110xx0 is transferred from the
(3) Since the processing after the INTIIC signal occurs differs according to the data that follows the extension code,
Remark
2
C bus mode, the status of the serial data bus (SDA) during data transmission is captured by the IIC0 register of
for extension code reception and an interrupt request signal (INTIIC) is issued at the falling edge of the eighth
clock.
The local address stored in the SVA0 register is not affected.
master device, the results are as follows. Note that the INTIIC signal occurs at the falling edge of the eighth
clock.
• Higher 4 bits of data match: IICS0.EXC0 bit = 1
• 7 bits of data match: IICS0.COI0 bit = 1
such processing is performed by software. The slave that has received an extension code is always under
communication, even if the addresses mismatch.
For example, when operation as a slave is not desired after the extension code is received, set the
IICC0.LREL0 bit to 1 and the CPU will enter the next communication wait state.
0000
1111
1111
Error Detection
Extension Code
Slave Address
2
C bus mode, the master device can select a particular slave device by transmitting the corresponding
000
0xx
0xx
For the extension codes other than above, see the I
Semiconductors.
R/W Bit
Table 17-4. Bit Definitions for Major Extension Code
0
0
1
General call address
matches)
10-bit slave address specification (upon address authentication)
10-bit slave address specification (upon read command issuance after address
User’s Manual U18279EJ3V0UD
CHAPTER 17 I
2
C BUS
2
C bus specifications issued by NXP
Description
905